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MT9V403 Datasheet(PDF) 21 Page - Micron Technology

Part No. MT9V403
Description  1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9V403 Datasheet(HTML) 21 Page - Micron Technology

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1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
09005aef80c07280
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V403_DS.fm - Rev. B 1/04 EN
21
©2004 Micron Technology. Inc.
Gain Settings
There are four independent gain controls which are
programmed via the two-wire serial interface. The four
gains correspond to four cells of the Bayer pattern
color filter array: red, green1, blue, and green2. The
gain step size can be set to 1 or 0.5. When the step size
is 1 the gain can programmed in 18 steps from X1 to
X18. When the step size is 0.5, the gain can be pro-
grammed 18 steps from X1 to X9. Global gain control is
achieved by changing the four gains equally and
simultaneously.
To obtain the desired analog signal chain gain, set
the following registers as shown in Table 6.
Analog Biases
VLN1, VLP, VOFF, VREF, VREF1, VLN2 VREF2,
VLN_AMP, and VLN_OUT are generated on-chip and
can be adjusted via a two-wire serial interface. Also,
the user may disable internal bias via a two-wire serial
interface and apply external voltages to the sensor.
VREF1DRV is generated on-chip but its internal bias
cannot be disabled. VRST_PIX and VRSTLOW are not
generated internally and external voltages must be
applied.
Considerations when Setting Analog
Voltages
The starting point for setting the analog voltages
should be the values suggested in the typical values
columns of the Tables 7 and 8. Additionally, Figure 21
on page 17, the “Signal Path Diagram,” indicates how
the analog voltages affect the image. Other consider-
ations follow:
VRSTLOW: Functions as a pixel anti-blooming con-
trol. For high illumination conditions (typically used in
conjunction with a short integration time) black/white
spots may appear. To eliminate these artifacts, this
voltage should be set to ~0.4V. Once set, this value
should not have to be changed for different imaging
conditions.
VLN2: Internal default value should be used as the
starting point. VLN2 controls the current in the ADC
comparators and there is a safe range where this volt-
age has no effect; settings below this range will cause
the comparators to fail. For high-speed operation,
VLN2 may need to be increased to remove random
white spots. VLN2 may be further increased with regis-
ter 17 by setting bit 0 to “1.” If this does not completely
solve the problem, set bit 7 in register 18 to disable
VLN_OUT.
VRST_PIX: Should be set to 2.5V.
VREF2: Internal default value is recommended.
VLN1: Internal default value is recommended.
VOFF: Internal default value is recommended.
VREF1: Internal default value is recommended.
VLP: Internal default value is recommended.
VLN_OUT: Internal default value is recommended.
VLN_AMP: Internal default value is recommended.
VREF: Internal default value is recommended.
ADC Calibration
The MT9V403 contains a special self-calibrating cir-
cuitry that enables it to reduce its own column-wise
fixed-pattern noise. This calibration process consists
of connecting a calibration signal to each of the 167
ADC inputs and estimating and storing these 167 off-
sets (as 7 bits) to subtract from subsequent samples.
Self-calibration automatically occurs after global logic
reset (LRST_N) or the two-wire serial interface (register
12), and programs new offset values for each ADC into
calibration memory. These values may be different
from those calculated in the previous calibration if
there has been a change in environment (e.g., temper-
ature). The accuracy of calibration is approximately
1mVrms.


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