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MT9V403 Datasheet(PDF) 2 Page - Micron Technology

Part No. MT9V403
Description  1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9V403 Datasheet(HTML) 2 Page - Micron Technology

 
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1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
09005aef80c07280
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V403_DS.fm - Rev. B 1/04 EN
2
©2004 Micron Technology. Inc.
Figure 1: Block Diagram
Reset
Expose
Frame
Row
Sensor
Interface
Block
Control
Logic
Row
Decoder
Pixel Array
Column PGA
Column ADCs and
calibration memory
667H x 10 SRAM (x2)
ADC and Output Registers
Gain Control
Calibration Data
Readout Control
Two-Wire
Serial
Interface
Output (9:0)
System
Clock
System
Clock
System
Data
Table 1:
Pin Description
PIN
NUMBERS
SIGNAL NAME
TYPE
DESCRIPTIONS
37
SYSCLK
Input
Clock input for entire chip. Maximum design frequency is 66 MHz (50 percent,
±5 percent duty cycle).
33
LRST_N
Input
Global logic RESET function (asynchronous). Active low pulse with minimum
duration 200ns.
30
ROW_STRT
Input
Slave mode input signal. Starts row processing sequence of the pixel row (i.e.,
pixel readout, ADC conversion, and writing of data to ADC registers). The rising
edge of ROW_STRT should be synchronous with the falling edge of SYSCLK. A
one-clock cycle wide active high pulse. The two-wire serial interface register
setting switches this pin between input and output.
31
LD_SHFT_N
Input
Slave mode input signal. An active LOW signal that enables the column counter
and initiates the readout process. Causes the 10-bit output port to be updated
with data on the rising edge of the system clock. The two-wire serial interface
register setting switches this pin between input and output.
29
EXPOSE
Input
Trigger for snapshot mode. The two-wire serial interface register setting
switches this pin between input and output. No connection should be made in
slave mode.
26
PG_N
Input
Slave mode input signal. Active low pulse that resets all photodetectors,
starting a new integration cycle. No connection should be made in master
mode or snapshot mode.
25
TX_N
Input
Slave mode input signal. Active low pulse that controls transfer of charge from
photodetector to memory inside each pixel for the entire pixel array. No
connection should be made in master mode or snapshot mode.
24
RESMEM
Input
Slave mode input signal. Active low pulse to reset all pixel memories. No
connection should be made in master mode or snapshot mode.
38
SCLK
Input
Serial port clock. Maximum frequency is 1 MHz.
18
VLNS
Input
Bias setting voltage for VLN_AMP or VLN_OUT. VLN_AMP and VLN_OUT can be
individually disconnected from their internal biases via the two-wire serial
interface and driven by this input.
17
VLN1
Input
Bias setting voltage for pixel source following operating current.
19
VLP
Input
Bias setting voltage for the column source follower operating current.
13
VOFF
Input
Dark offset cancellation. Polarity of offset is set via the two-wire serial
interface.
16
VREF
Input
Op amp bias.


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