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MT9V111 Datasheet(PDF) 5 Page - Micron Technology

Part No. MT9V111
Description  1/4-Inch SOC VGA CMOS Active-Pixel Digital Image Sensor
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9V111 Datasheet(HTML) 5 Page - Micron Technology

 
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V111_2.fm - Rev. G 1/05 EN
5
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
General Description
General Description
This SOC VGA CMOS image sensor features DigitalClarity
Micron’s breakthrough,
low-noise CMOS imaging technology that achieves CCD image quality (based on signal-
to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost and
integration advantages of CMOS.
The MT9V111 is a fully-automatic, single-chip camera, requiring only a power supply,
lens and clock source for basic operation. Output video is streamed via a parallel eight-
bit DOUT port as shown in Figure 1. Output pixel clock is used to latch the data, while
FRAME_VALID and LINE_VALID signals indicate the active video. The sensor can be put
in an ultra-low power sleep mode by asserting the STANDBY pin. Output pads can also
be tri-stated by de-asserting the OE# pin. The MT9V111 internal registers can be config-
ured using a two-wire serial interface.
The MT9V111 can be programmed to output progressive scan images up to 30 fps in an
8-bit ITU_R BT.656 (YCbCr) formerly CCIR656, YUV, 565RGB, 555RGB, or 444RGB for-
mats. The FRAME_VALID and LINE_VALID signals are output on dedicated pins, along
with a pixel clock that is synchronous with valid data.
Figure 1: Chip Block Diagram
The MT9V111 can accept the input clock of up to 27 MHz, delivering 30 fps. With power-
on defaults (see Appendix B for recommended defaults), the camera is configured to
deliver 15 fps at 12 MHz and automatically slows down the frame rate in low-light condi-
tions to achieve longer exposures and better image quality.
Internally, the MT9V111 consists of a sensor core and an image flow processor. The sen-
sor core functions to capture raw Bayer-encoded images that are input into the IFP as
shown in Figure 1. The IFP processes the incoming stream to create interpolated, color-
corrected output and controls the sensor core to maintain the desirable exposure and
color balance.
Sensor core and IFP registers are grouped into two separate address spaces, as shown in
Figure 2. The internal registers can be accessed via the two-wire serial interface. Select-
ing the desired address space can be accomplished by programming register R1 which
remains present in both register sets.
DOUT(7:0)
PIXCLK
FRAME_VALID
LINE_VALID
FLASH
Communication Bus
Sensor Core
. Based on MT9V011
. 668H x 496V (VGA+ Reference)
. 1/4-inch optical format
. Auto Black compensation
. Programmable analog gain
. Programmable exposure
. Low power, 10-bit ADCs
SRAM Line Buffers
Image Flow Processor
. Color correction, gamma,
lens shading correction
. Auto exposure, white balance
. Interpolation and defect
correction
. Flicker avoidance
SCLK
SDATA
SADDR
CLK
STANDBY
OE#
VDD/DGND
VAA/AGND
VAAPIX


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