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MT9V111 Datasheet(PDF) 42 Page - Micron Technology

Part No. MT9V111
Description  1/4-Inch SOC VGA CMOS Active-Pixel Digital Image Sensor
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9V111 Datasheet(HTML) 42 Page - Micron Technology

 
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V111_2.fm - Rev. G 1/05 EN
42
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Appendix B – Overview Of Programming
Appendix B – Overview Of Programming
Default Sensor Configuration
In its default configuration, the sensor outputs up to 15 fps at 12 MHz master clock fre-
quency. Auto exposure, automatic white balance, 60Hz flicker avoidance, defect correc-
tion, and automatic noise suppression in low light conditions are enabled. The frame
rate is controlled by AE and can be slowed down to 5 fps in low light. Lens shading cor-
rection is disabled. Gamma correction uses gamma = 0.6. Image data are output in
YCbCr ITU_R.BT.656 VGA format, with Y, Cb, and Cr values ranging from 16 to 240.
The use of the non-default register settings shown in Table 14 are recommended to opti-
mize sensor performance in the above configuration.
Note:
Non-default register settings required for an optimal 30 fps, 27 MHz operation are shown
in Table 15
Note:
To obtain register settings for other frame rates and clock speeds, please contact a Micron
FAE.
Auto Exposure
Target image brightness and accuracy of AE are set by IFP R46[7:0] and R46[15:8],
respectively. For example, to overexpose images, set IFP R46[7:0] = 120. To change
image brightness on LCD in RGB preview mode, use IFP R52[15:8]. AE logic can be pro-
grammed to keep the frame rate constant or vary it within certain range, by writing to
IFP R55[9:5] one of the values tabulated in Table 16.
The speed of AE is set using IFP R47. The speed should be high in preview modes and
lower for video output to avoid sudden changes in brightness between frames.
Auto exposure is disabled by setting IFP R6[14] = 0. When AE, AWB, and flicker avoid-
ance are all disabled (IFP R6[14] = 0, IFP R6[1] = 0, and IFP R8[11] = 0), exposure and ana-
log gains can be adjusted manually (see core registers R9, R12, and R43 through R46).
Table 14: Non-Default Register Settings Optimizing 15 fps at 12 MHz Operation
Core:
R5 = 46, R7[4] = 0, R33 = 58369, R47 = 63414
IFP:
R51= 5137, R56 = 2168, R57= 290, R59 = 1068, R62 = 4095, R64 = 7696, R65 = 5143,
R66 = 4627,
R67 = 4370, R68 = 28944, R69 = 29811
Table 15: Non-Default Register Settings Optimizing 30 fps at 27 MHz Operation
Core:
R5 = 132, R6 = 10, R7[4] = 0, R33 = 58369
IFP:
R51 = 5137, R57 = 290, R59 = 1068, R62 = 4095, R89 = 504, R90 = 605, R92 = 8222,
R93 = 10021,
R100 = 4477
Table 16: Relation Between IFP R55[9:5] Setting and Frame Rate Range
Minimum Frame
Rate
Maximum Frame Rate = 15 fps
Maximum Frame Rate =
30 fps
30 fps
N/A
4
15 fps
8
8
7.5 fps
16
16
5 fps
24
24


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