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MT9V111 Datasheet(PDF) 36 Page - Micron Technology

Part No. MT9V111
Description  1/4-Inch SOC VGA CMOS Active-Pixel Digital Image Sensor
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9V111 Datasheet(HTML) 36 Page - Micron Technology

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Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V111_2.fm - Rev. G 1/05 EN
36
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Serial Bus Description
Serial Bus Description
Registers are written to and read from the MT9V111 through the two-wire serial inter-
face bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK),
which is driven by the serial interface master. Data is transferred into and out of the
MT9V111 through the serial data (SDATA) line. The SDATA line is pulled up to 2.8V off-
chip by a 1.5KΩ resistor. Either the slave or master device can pull the SDATA line down—
the serial interface protocol determines which device is allowed to pull the SDATA line
down at any given time. The registers are 16 bits wide and can be accessed through 16-
bit or eight-bit two-wire serial bus sequences.
Protocol
The two-wire serial interface defines several different transmission codes, as follows:
•a start bit
• the slave device eight-bit address. SADDR is used to select between two different
addresses in case of conflict with another device. If SADDR is LOW, the slave address is
0x90; if SADDR is HIGH, the slave address is 0xB8.
• a(n) (no) acknowledge bit
• an eight-bit message
•a stop bit
Sequence
A typical read or write sequence begins by the master sending a start bit. After the start
bit, the master sends the slave device's eight-bit address. The last bit of the address
determines if the request will be a read or a write, where a "0" indicates a write and a "1"
indicates a read. The slave device acknowledges its address by sending an acknowledge
bit back to the master.
If the request was a write, the master then transfers the 8-bit register address to which a
write should take place. The slave sends an acknowledge bit to indicate that the register
address has been received. The master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each 8 bits. The MT9V111 uses 16-bit data for
its internal registers, thus requiring two eight-bit transfers to write to one register. After
16 bits are transferred, the register address is automatically incremented, so that the
next 16 bits are written to the next register address. The master stops writing by sending
a start or stop bit.
A typical read sequence is executed as follows. First the master sends the write-mode
slave address and eight-bit register address, just as in the write request. The master then
sends a start bit and the read-mode slave address. The master then clocks out the regis-
ter data eight bits at a time. The master sends an acknowledge bit after each eight-bit
transfer. The register address is auto-incremented after every 16 bits is transferred. The
data transfer is stopped when the master sends a no-acknowledge bit.
The MT9V111 allows for eight-bit data transfers through the two-wire serial interface by
writing (or reading) the most significant eight bits to the register and then writing (or
reading) the least significant eight bits to Reg0x7F (127).
Bus Idle State
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-
ated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
Start Bit
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line
is HIGH.


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