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MT9V111 Datasheet(PDF) 20 Page - Micron Technology

Part No. MT9V111
Description  1/4-Inch SOC VGA CMOS Active-Pixel Digital Image Sensor
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9V111 Datasheet(HTML) 20 Page - Micron Technology

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Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V111_2.fm - Rev. G 1/05 EN
20
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register Description
127
0x7F
7:0
0
Eight-bit, Two-wire serial interface helper.
Internal MT9V111 registers are up to 16-bit wide. To execute 16-bit reads and writes, eight-bit two-wire serial
interface devices need special handling by using Reg0x7F. A 16-bit write is done by writing the upper eight
bits to the desired register and then writing the lower eight bits to Reg0x7F. The register is not updated until
all 16 bits have been written. It is not possible to just update half a register. To read eight-bytes at a time,
read the upper eight bits from the desired register; then read the lower eight bits from Reg0x7F.
152
0x98
15:0
1040
Flash control.
7:0
16
Strobe duration, x512 CLK_IN. Value of 255 is special, enabling infinite duration.
80
Invert pin state.
90
“1” = fire every frame continuously.
“0” = fire only once per arming.
10
1
Strobe source select.
“1” = end of shutter enable.
“0” = end of frame enable.
12:11
0
Delay; skips programmed number of frames after arming and before firing.
13
0
Write “1” to arm flash and set it to fire. Flash will fire after delay set in Reg0x98 [12-11].
14
R/O
“1” = Flash has fired in current frame.
15
R/O
State of the output flash pin.
The flash control supports both Xenon and LED light sources using a dedicated output pad. For Xenon flashes
the pad generates a strobe to fire when the imager's shutter is fully open. For LED the pad can be asserted or
de-asserted asynchronously. To turn LED off and on program Reg0x98 [8]. To fire a Xenon flash, arm the
strobe trigger by setting Reg0x98 [13]=1. The strobe will appear when the shutter fully opens. Strobe length
is set by Reg0x98 [7-0]. Other available modes include continuous vs. single firing and skipping a
programmable number of frames after arming and before firing.
153
0x99
12:0
R/O
Line counter.
Use line counter to determine the number of line currently being output.
154
0x9A
15:0
R/O
Frame counter.
Use frame counter to determine number of frames output so far.
165
0xA5
15:0
0
Horizontal pan in decimation.
9:0
0
Horizontal pan.
15
W/O
“1” = freeze update of decimation parameters.
Decimation control registers work to downsize output image to any size. The output image size is specified in
Reg0xA7 and Reg0xAA for horizontal and vertical directions respectively. For example, to downsize the VGA
output to QQVGA set Reg0xA7 = 160 and Reg0xAA = 20. Whenever output image is downsized, the zoom
feature becomes available. To zoom in, program Reg0xA6 and Reg0xA9 with the size of window to be
decimated. For example, in QQVGA setting Reg0xA6 = 320 and Reg0xA9 = 240 results in 2X zoom. Here the
output image of 160 x 120 is created from a pre-decimation window of 320 x 240 instead of the full VGA 640
x 480. Whenever the output image is zoomed, pan controls become available. To pan a zoomed image
program Reg0xA5 and Reg0xA8 to offset the pre-decimation window in to the right and bottom respectively.
When implementing a smooth zoom and pan, it is useful to synchronize the update of all decimation
registers to avoid jerks in the output video. When writing a batch of decimation settings, set bit 15 of each
datum to”1” to freeze the update. Set bit 15 of the last datum in the batch to “0” to enable normal
operation. The entire batch of decimation settings will then be synchronously loaded on the next frame start.
166
0xA6
15:0
640
Horizontal zoom in decimation.
9:0
640
Horizontal size of window before decimation.
15
W/O
“1” = freeze update of decimation parameters.
See R0xA5 for details.
Table 7:
IFP Register Description (Continued)
Register
Bits
Default
Name


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