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MT9V111 Datasheet(PDF) 19 Page - Micron Technology

Part No. MT9V111
Description  1/4-Inch SOC VGA CMOS Active-Pixel Digital Image Sensor
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9V111 Datasheet(HTML) 19 Page - Micron Technology

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Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V111_2.fm - Rev. G 1/05 EN
19
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register Description
52
0x34
15:0
16
Luminance offset control. Use this register to adjust LCD brightness.
7:0
16
Y offset in YCbCr mode.
15:8
0
Offset in RGB mode.
This register specifies constant offset added to the luminance or RGB components prior to the output. Use
this register to adjust LCD brightness.
53
0x35
15:0
61456
Clipping limits for output luminance.
7:0
16
Lowest value of output luminance.
15:8
240
Highest value of output luminance.
This register specifies upper and low limits to which the output YCbCr data is clipped.
58
0x3A
7:0
0
Output format control 2.
00
In YUV output mode swaps Cb and Cr channels. In RGB, swaps R and B. This bit is
subject to synchronous update.
10
Swap chrominance byte with luminance byte in YCbCr/YUV output. In RGB, swap odd
and even bytes. This bit is subject to synchronous update.
20
Average two nearby chrominance bytes.
4:3
0
Test ramp output:
“00”
off.
“01”
by column.
“10”
by row.
“11”
by frame.
50
Output R,G,B or Cr,Y,Cb values are shifted 3 bits up; use with Reg0x3A[4:3] to test LCDs
with low color depth.
7:6
0
RGB output format:
“00” = 16-bit RGB565.
”01” = 15-bit RGB555.
“10” = 12-bit RGB444.
“11” = 12-bit RGBx444.
72
0x48
7:0
0
Test pattern generator.
2:0
0
Test pattern selection.
70
“1”
force WB digital gains to 1.0.
This register enables color bar test-pattern generation at the input of the image processor. Values greater
than "0" turn test pattern generation on. The brightness of the flat-color areas depends on the value
programmed in this register.
91
0x5B
2:0
2
Flicker control.
00
“1”
manual mode.
“0”
auto flicker detection.
11
If R0x5B [0] = “1” then '“0”- 50Hz AC; “1”- 60Hz AC.
98
0x62
15:0
4112
AE digital gains.
7:0
16
Current digital gain applied before lens shading correction.
15:8
16
Current digital gain applied during lens shading correction.
When R6 [14] = 1, registers are read-only and show current digital gains. When R6 [14] = 0, writing into
registers sets current digital gains. LC digital gain, R98 [15:8], is unity if LC is disabled, R8 [8] = 0. The
combined gain of R98 [15:8] and LC must be less than 16. See also R103.
103
0x67
15:0
16400
AE digital gains limits.
7:0
16
Maximal digital gain applied before lens shading correction.
15:8
64
Maximal digital gain applied during lens shading correction.
Value 16 corresponds real digital gain of 1.0. As AE increases gain in dark conditions, pre-LC gain is used first.
Post-LC gain is used only after pre-LC gain reaches its maximum allowed limit. See also R98.
Table 7:
IFP Register Description (Continued)
Register
Bits
Default
Name


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