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MT9V111 Datasheet(PDF) 7 Page - Micron Technology

Part No. MT9V111
Description  1/4-Inch SOC VGA CMOS Active-Pixel Digital Image Sensor
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9V111 Datasheet(HTML) 7 Page - Micron Technology

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Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V111_2.fm - Rev. G 1/05 EN
7
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Ball Assignment
Ball Assignment
Figure 4: 44-Ball ICSP Package
Table 2:
Ball Description
Ball
Numbers
Name
Type
Description
G2
CLKIN
Input
Master Clock into sensor. Default is 12 MHz (27 MHz maximum).
F3
SCLK
Input
Serial Clock.
F4
SADDR
Input
Serial Interface address select: Reg0xB8 when HIGH (default).
Reg0x90 when LOW.
F6
ADC_TEST
Input
Tie to VAAPIX (factory use only).
E6
RESET#
Input
Asynchronous reset of sensor when LOW. All registers assume factory defaults.
E7
STANDBY
Input
When HIGH puts the imager in ultra-low power standby mode.
D6
OE#
Input
Output_Enable_Bar pin. When HIGH tri-state all outputs except SDATA (tie
LOW for normal operation).
C6
SCAN_EN
Input
Tie to Digital ground.
G3
SDATA
I/O
Serial data I/O.
E2
FLASH
Output
Flash Strobe.
E1
PIXCLK
Output
Pixel Clock Out. Pixel data output are valid during rising edge of this clock. IFP
Reg0x08 [9] inverts polarity.
Frequency = Master Clock.
E3
LINE_VALID
Output
Active HIGH during line of selectable valid pixel data.
F1
FRAME_VALID
Output
Active HIGH during frame of valid pixel data.
B5
DOUT7
Output
ITU_R BT.656/RGB data bit 7 (MSB).
A
B
C
D
E
F
G
2
DOUT2
VDD
DOUT0
NC
FLASH
VDD
CLKIN
3
DOUT4
DOUT3
DOUT5
LINE_
SCLK
SDATA
1
DGND
DOUT1
NC
DGND
PIXCLK
FRAME_
VALID
DGND
4
DGND
VDD
SADDR
DGND
6
VDD
VDD
SCAN
OE#
RESET#
ADC_
VAA
7
DGND
VDD
DGND
DGND
STAND
VAAPIX
AGND
5
DOUT6
DOUT7
VDD
VDD
AGND
VAA
Top View
(Ball Down)
BY
VALID
_EN
TEST


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