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MT9V012 Datasheet(PDF) 6 Page - Micron Technology

Part No. MT9V012
Description  1/6-Inch VGA CMOS Digital Image Sensor
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT9V012 Datasheet(HTML) 6 Page - Micron Technology

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Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V012_2.fm - Rev. B 2/05 EN
6
©2004 Micron Technology, Inc. All rights reserved.
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
Functional Overview
Preliminary
Figure 1: Block Diagram
Functional Overview
The MT9V012 is a progressive-scan sensor that generates a stream of pixel data qualified
by LINE_VALID and FRAME_VALID signals. It uses an input master clock of 27 MHz
(nominal). The data rate (pixel clock) is one half of the master clock frequency, which
means that one pixel is generated every two master clock cycles. Figure 1 shows the sen-
sor block diagram.
The core of the sensor is an active-pixel array. The timing and control circuitry
sequences through the rows of the array, resetting and then reading each row in turn. In
the time interval between resetting a row and reading that row, the pixels in that row
integrate incident light. The exposure is controlled by varying the time interval between
reset and readout. Once a row has been read, the data from the columns is sequenced
through an analog signal chain (providing offset correction and gain), and then through
an ADC. The output from the ADC is a 10-bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain (which provides further offset
correction, applies digital gain, and may perform pixel defect correction).
The pixel array contains optically active and light shielded (“black”) pixels. The black
pixels are used to provide data for on-chip offset correction algorithms (“black level”
control).
The sensor contains a set of 16-bit control and status registers that can be used to con-
trol many aspects of the sensor behavior. These registers can be accessed through a two-
wire serial interface. In this document, registers are specified either by name (e.g., col-
umn start) or by register address (e.g., Reg0x04). Fields within a register are specified by
bit or by bit range (e.g., Reg0x20[0] or Reg0x0B[13:0]). Table 6, Register Description, on
page 23, describes the control and status registers.
The output from the sensor is a Bayer pattern: alternate rows are a sequence of either
green/red pixels or blue/green pixels. The offset and gain stages of the analog signal
chain provide per-color control of the pixel data.
The MT9V012 supports two different functional modes of operation:
• Default mode: the sensor generates a VGA-sized image by default, with 10 parallel
data outputs per pixel, and separate LINE_VALID, FRAME_VALID, and PIXCLK out-
puts. All timing control is performed on-chip.
• Serial mode: the sensor generates a VGA-sized image by default. Pixel data,
LINE_VALID, and FRAME_VALID are encoded into a single serial data stream that
uses a two-signal low-voltage differential signalling (LVDS) interface. All timing con-
trol is performed on-chip.
Active-Pixel
Sensor (APS)
Array
Serial
I/O
Data
Out
Sync
Signals
Timing and Control
Control Register
Analog Processing
ADC


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