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MT9D011 Datasheet(PDF) 53 Page - Micron Technology |
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MT9D011 Datasheet(HTML) 53 Page - Micron Technology |
53 / 61 page MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR PRELIMINARY 09005aef81516da4 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 53 ©2004 Micron Technology, Inc. All rights reserved. Power-Saving Modes The sensor can be placed in a low power standby state by either of these mechanisms: • Asserting STANDBY input pin (provided that Reg0x0D[7] = 0) • Setting Reg0x0D[2] = 1 by performing a register write through the serial register interface. These two methods are equivalent and have the same effect: • The source of standby is synchronized and latched. Once latched, the full standby sequence is completed even if the source of standby is removed. • The readout of the current row is completed. • Internal clocks are gated off. • The analog signal chain and associated current and voltage sources are placed in a low power state. The standby state is maintained for as long as the standby source remains asserted. Table 15 shows the state of the pin interface while in standby state. Output-enable control can be used to place the pin interface in a high-impedance state (see “Output Enable Control” on page 51). While in standby, the state of the internal registers is maintained and the sensor continues responding to accesses through its serial register interface. An even lower power standby state can be achieved by stopping the input clock (CLKIN) while in standby. If the input clock is stopped, the sensor does not respond to accesses through its serial register interface. Exit from standby must be through the same mech- anism as entry to standby. When the standby source is negated, this sequence occurs: 1. The internal clocks are restarted. 2. The analog circuitry is restored to its normal oper- ating state. 3. The timing and control circuitry performs a restart equivalent to writing Reg0x0D[1] = 1. After this sequence is complete, normal operation resumes. If the input clock is stopped during standby, it must be restarted before leaving standby. PLL and Standby If the PLL is used to generate master clock, special care must be taken when entering standby mode. The PLL uses relatively high power, so allowing the PLL to power down during standby is recommended. This can be controlled in Reg0x65[13]. By default the PLL powers down whenever MT9D011 enters standby. The operation of the circuit cannot be guaranteed if the PLL is driving the master clock when it powers down. To safely allow the PLL to power down when enter- ing standby, turn on PLL bypass before triggering standby (controlled by Reg0x65[15]). When coming out of standby mode, the normal PLL power-up sequence must be followed as specified in “PLL Power-up” on page 36. Floating Inputs Many MT9D011 signals use bi-directional pins (shown in Table 4 on page 12) for the following three reasons: • The signal associated with the pin is bi-directional in normal use (the only signal in this category is SDATA). • The pin is normally used as an output, but is used as an input during manufacturing test modes (e.g., DOUT[9:0]). • Standard design practice dictates that signal inputs should not be allowed to float for long periods of time. This leads to two areas where the design application should be reviewed: • When using the output-enable control. All MT9D011 bi-directional pins that enter a high- impedance state must be driven to a valid logic level. ( “Output Enable Control” on page 51.) • When input pins are allowed to float. The MT9D011 does not include on-chip pull-down resistors, therefore, no input pins should be allowed to float. Dark Row/Column Display Optically black rows 7 through 0 are used to provide data for black level calibration and are not normally visible in the displayed image. Setting Reg0x22[7] = 1 makes these rows visible in the displayed image. This is achieved by asserting FRAME_VALID earlier than normal, and keeping it asserted longer, so that the fol- lowing rows are displayed: • The optically black rows at the start of the pixel array (controlled by Reg0x22[2:0]). • Two rows before the visible rows. • The visible rows (controlled by Reg0x01, Reg0x03 and Reg0x20). Table 15: Signal State During Standby SIGNAL STATE LINE_VALID 0 FRAME_VALID 0 LINE_VALID 0 PIXCLK 0 FLASH 0 DOUT9–DOUT0 0 |
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