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MT9D011 Datasheet(PDF) 43 Page - Micron Technology

Part # MT9D011
Description  1/3-INCH 2-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT9D011 Datasheet(HTML) 43 Page - Micron Technology

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MT9D011
2-MEGAPIXEL DIGITAL IMAGE SENSOR
PRELIMINARY
09005aef81516da4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN
43
©2004 Micron Technology, Inc. All rights reserved.
Frame Rate Control
For a given window size, the blanking registers
(Reg0x05-Reg0x08) along with the row speed register
(Reg0x0A) can be used to set a particular frame rate.
The frame timing equations (Table 3 and Table 4 on
page 12) can be rearranged to express the horizontal
blanking or vertical blanking values as a function of
the frame rate:
The HBLANK_REG value allows the frame rate to be
adjusted
with
a
minimum
resolution
of
one
PIXCLK_PERIOD multiplied by the total number of
rows (displayed plus blanking). When finer resolution
is required, Reg0x0b (Extra Delay) can be used.
Reg0x0b allows the frame time to be changed in incre-
ments of pixel clocks.
Minimum Horizontal Blanking
The minimum horizontal blanking value is con-
strained by the time used for sampling a row of pixels
and the overhead in the row readout. This is expressed
in Table 10.
Minimum Row Time Requirement
The total row time must be sufficient to allow all row
operations (readout and shutter operations). The row
time is the sum of column width (halved during bin-
ning divided by column skip factor) and horizontal
blanking, and can therefore be adjusted by program-
ming these.
Table 11 shows minimum row time as a function of
mode of operation.
Note that this is a particularly strict requirement
during binning because twice as many row operations
are required per row and the column width is halved.
HBLANK_REG = master clock freq / (frame rate*
((Reg0x03/S + BORDER) + VBLANK_REG)*PIXCLK_PERIOD) - (Reg0x04/S + BORDER)
VBLANK_REG = master clock freq / (frame rate*
((Reg0x04/S + BORDER) + HBLANK_REG)*PIXCLK_PERIOD) - (Reg0x03/S + BORDER)
Table 10:
Minimum Horizontal Blanking Parameters
PARAMETER
DEFAULT /
2 ADC MODE,
NO BINNING
1 ADC MODE,
NO BINNING
2 ADC MODE,
BINNING
1 ADC MODE,
BINNING
HBLANK(MIN)
286 mclks
324 mclks
= 162 pixclks
470 mclks
508 mclks
= 254 pixclks
Table 11:
Minimum Row Time Parameters
PARAMETER
DEFAULT /
2 ADC MODE,
NO BINNING
1 ADC MODE,
NO BINNING
2 ADC MODE,
BINNING
1 ADC MODE,
BINNING
ROW_TIME(MIN)
473 mclks
488 mclks
= 244 pixclks
931 mclks
946 mclks =
473 pixclks
pointer_operations 461 mclks
464 mclks
919 mclks
922 mclks


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