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EVAL-AD7616-PSDZ Datasheet(PDF) 7 Page - Analog Devices |
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EVAL-AD7616-PSDZ Datasheet(HTML) 7 Page - Analog Devices |
7 / 47 page AD7616-P Data Sheet Rev. 0 | Page 6 of 46 TIMING SPECIFICATIONS Note that throughout the timing specifications, multifunction pins, such as WR/ BURST, are referred to either by the entire pin name or by a single function of the pin, for example, WR, when only that function is relevant. Universal Timing Specifications VCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 3.6 V, VREF = 2.5 V external reference/internal reference, TA = −40°C to +125°C, unless otherwise noted. Interface timing tested using a load capacitance of 30 pF. Table 2. Parameter1 Min Typ Max Unit Description t CYCLE 1 µs Minimum time between consecutive CONVST rising edges (excluding burst and oversampling modes) t CONV_LOW 50 ns CONVST low pulse width t CONV_HIGH 50 ns CONVST high pulse width t BUSY_DELAY 34 ns CONVST high to BUSY high (manual mode) t CS_SETUP 20 ns BUSY falling edge to CS falling edge setup time t CH_SETUP 50 ns Channel select setup time in hardware mode for CHSELx t CH_HOLD 20 ns Channel select hold time in hardware mode for CHSELx t CONV 475 530 ns Conversion time for the selected channel pair t ACQ 470 ns Acquisition time for the selected channel pair t QUIET 50 ns CS rising edge to next CONVST rising edge t RESET_LOW See Figure 3 Partial Reset 40 500 ns Partial RESET low pulse width Full Reset 1.2 µs Full RESET low pulse width t DEVICE_SETUP See Figure 3 Partial Reset 120 ns Time between partial RESET high and CONVST rising edge Full Reset 15 ms Time between full RESET high and CONVST rising edge t WRITE See Figure 3 Partial Reset 50 ns Time between partial RESET high and CS for write operation Full Reset 240 µs Time between full RESET high and CS for write operation t RESET_WAIT 1 ms Time between stable V CC/VDRIVE and release of RESET (see Figure 3) t RESET_SETUP Time prior to release of RESET that queried hardware inputs must be stable for (see Figure 3) Partial Reset 10 ns Full Reset 0.05 ms t RESET_HOLD Time after release of RESET that latched hardware inputs must be stable for (see Figure 3) Partial Reset 10 ns Full Reset 0.24 ms 1 Not production tested. Sample tested during initial release to ensure compliance. Figure 2. Universal Timing Diagram Across All Interfaces CHSEL0 TO CHSEL2 CS BUSY CONVST CHX tCH_SETUP tCH_HOLD tCS_SETUP tACQ tCONV tCONV_HIGH tCONV_LOW tCYCLE tBUSY_DELAY tQUIET CHY HARDWARE MODE ONLY |
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