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AD7617BSTZ-RL Datasheet(PDF) 9 Page - Analog Devices |
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AD7617BSTZ-RL Datasheet(HTML) 9 Page - Analog Devices |
9 / 52 page AD7617 Data Sheet Rev. 0 | Page 8 of 51 Figure 4. Parallel Read Timing Diagram Figure 5. Parallel Write Timing Diagram Serial Mode Timing Specifications Table 4. Parameter Min Typ Max Unit Description fSCLK1 40/50 MHz SCLK frequency tSCLK 1/fSCLK Minimum SCLK period tSCLK_SETUP1 10.5 ns CS to SCLK falling edge setup time, VDRIVE above 3 V 13.5 ns CS to SCLK falling edge setup time, VDRIVE above 2.3 V tSCLK_HOLD 10 ns SCLK to CS rising edge hold time tSCLK_LOW 8 ns SCLK low pulse width tSCLK_HIGH 9 ns SCLK high pulse width tDOUT_SETUP1 9 ns Data out access time after SCLK rising edge, VDRIVE above 3 V 11 ns Data out access time after SCLK rising edge, VDRIVE above 2.3 V tDOUT_HOLD 4 ns Data out hold time after SCLK rising edge tDIN_SETUP 10 ns Data in setup time before SCLK falling edge tDIN_HOLD 8 ns Data in hold time after SCLK falling edge tDOUT_3STATE 10 ns CS rising edge to SDOx high impedance 1 Dependent on VDRIVE and CLOAD (see Table 15). CONVST BUSY CS RD CONV A CONV B DB0 TO DB15 t RD_HOLD t RD_HIGH t DOUT_3STATE t RD_SETUP t RD_LOW t DOUT_SETUP CONVST CS WR WRITE REG 1 WRITE REG 2 DB0 TO DB15 tCONF_SETTLE tDIN_HOLD tDIN_SETUP tWR_HOLD tWR_SETUP tWR_HIGH tWR_LOW |
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