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AD4001 Datasheet(PDF) 31 Page - Analog Devices |
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AD4001 Datasheet(HTML) 31 Page - Analog Devices |
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31 / 37 page  Data Sheet AD4001/AD4005 Rev. B | Page 31 of 37 CS MODE, 3-WIRE WITH BUSY INDICATOR This mode is typically used when a single AD4001/AD4005 is connected to an SPI-compatible digital host with an interrupt input (IRQ). The connection diagram is shown in Figure 56, and the corresponding timing diagram is shown in Figure 57. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can select other SPI devices, such as analog multiplexers; however, CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up resistor of 1 kΩ on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD4001/AD4005 then enter the acquisition phase and power down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. If multiple AD4001/AD4005 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. There must not be any digital activity on the SCK during the conversion. SDI SDO CNV SCK CONVERT DATA IN CLK DIGITAL HOST VIO IRQ VIO 1kΩ AD4001/ AD4005 Figure 56. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) SDO D15 D14 D1 D0 tDIS SCK 12 3 15 16 17 tSCK tSCKL tSCKH tHSDO tDSDO CNV CONVERSION ACQUISITION tCONV tCYC ACQUISITION SDI = 1 tCNVH tACQ tQUIET2 Figure 57. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing Diagram (SDI High) |
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