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AD4001 Datasheet(PDF) 7 Page - Analog Devices

Part # AD4001
Description  Precision, Differential SAR ADCs
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4001 Datasheet(HTML) 7 Page - Analog Devices

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Data Sheet
AD4001/AD4005
Rev. B | Page 7 of 37
TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression
disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4001 and fS = 1 MSPS for the AD4005, unless otherwise
noted. See Figure 2 for the timing voltage levels.
Table 2. Digital Interface Timing
Parameter
Symbol
Min
Typ
Max
Unit
CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE
tCONV
270
290
320
ns
ACQUISITION PHASE1
tACQ
AD4001
290
ns
AD4005
790
ns
TIME BETWEEN CONVERSIONS
tCYC
AD4001
500
ns
AD4005
1000
ns
CNV PULSE WIDTH (CS MODE)2
tCNVH
10
ns
SCK PERIOD (CS MODE)3
tSCK
VIO > 2.7 V
9.8
ns
VIO > 1.7 V
12.3
ns
SCK PERIOD (DAISY-CHAIN MODE)4
tSCK
VIO > 2.7 V
20
ns
VIO > 1.7 V
25
ns
SCK LOW TIME
tSCKL
3
ns
SCK HIGH TIME
tSCKH
3
ns
SCK FALLING EDGE TO DATA REMAINS VALID DELAY
tHSDO
1.5
ns
SCK FALLING EDGE TO DATA VALID DELAY
tDSDO
VIO > 2.7 V
7.5
ns
VIO > 1.7 V
10.5
ns
CNV OR SDI LOW TO SDO D15 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE)
tEN
VIO > 2.7 V
10
ns
VIO > 1.7 V
13
ns
CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY
tQUIET1
190
ns
LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY5
tQUIET2
60
ns
CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE)
tDIS
20
ns
SDI VALID SETUP TIME FROM CNV RISING EDGE
tSSDICNV
2
ns
SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE)
tHSDICNV
2
ns
SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE)
tHSCKCNV
12
ns
SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)
tSSDISCK
2
ns
SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)
tHSDISCK
2
ns
1
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the
AD4001 and 1 MSPS for the AD4005.
2
For turbo mode, tCNVH must match the tQUIET1 minimum.
3
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
4
A 50% duty cycle is assumed for SCK.
5
See Figure 22 for SINAD vs. tQUIET2.
X% VIO1
Y% VIO1
VIH2
VIL2
VIL2
VIH2
tDELAY
tDELAY
1
FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 1.
Figure 2. Voltage Levels for Timing


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