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AD4000 Datasheet(PDF) 27 Page - Analog Devices

Part # AD4000
Description  Precision, Pseudo Differential, SAR ADCs
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4000 Datasheet(HTML) 27 Page - Analog Devices

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Data Sheet
AD4000/AD4004/AD4008
Rev. C | Page 27 of 36
STATUS WORD
The 6-bit status word can be appended to the end of a conversion
result, and the default conditions of these bits are shown in
Table 15. The status bits must be enabled in the register setting.
When the OV clamp flag is a 0, it indicates an overvoltage
condition. The OV clamp flag status bit updates on a per
conversion basis.
The SDO line returns to high impedance after the sixth status
bit is clocked out (except in daisy-chain mode). The user is not
required to clock out all status bits to start the next conversion.
The serial interface timing for CS mode, 3-wire without busy
indicator, including status bits, is shown in Figure 49.
SDO
D15
D14
D13
D1
D0
SCK
1
2
3
14
15
16
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CN V
CONVERSION
ACQUISITION
tCYC
ACQUISITION
SDI = 1
tCNVH
ACQ
tEN
21
22
tQUIET2
STATUS BITS[5:0]
B1
tDIS
B0
20
tCONV
Figure 49. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits (SDI High)
Table 15. Status Bits (Default Conditions)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OV clamp flag
Span compression
High-Z mode
Turbo mode
Reserved
Reserved


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