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AD4000 Datasheet(PDF) 18 Page - Analog Devices

Part # AD4000
Description  Precision, Pseudo Differential, SAR ADCs
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4000 Datasheet(HTML) 18 Page - Analog Devices

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AD4000/AD4004/AD4008
Data Sheet
Rev. C | Page 18 of 36
CONVERTER OPERATION
The AD4000/AD4004/AD4008 are SAR-based ADCs using a
charge redistribution sampling digital-to-analog converter
(DAC). Figure 31 shows the simplified schematic of the ADC.
The capacitive DAC consists of two identical arrays of 16 binary
weighted capacitors, which are connected to the comparator
inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via the SW+
and SW− switches. All independent switches connect the other
terminal of each capacitor to the analog inputs. The capacitor
arrays are used as sampling capacitors and acquire the analog
signal on the IN+ and IN− inputs.
When the acquisition phase is complete and the CNV input
goes high, a conversion phase initiates. When the conversion
phase begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. The differential voltage between the IN+ and
IN− inputs captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and VREF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4, …, VREF/65,536).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the control logic generates the
ADC output code and a busy signal indicator.
Because the AD4000, the AD4004, and the AD4008 have on-
board conversion clocks, the serial clock, SCK, is not required
for the conversion process.
TRANSFER FUNCTIONS
The ideal transfer characteristics for the AD4000/AD4004/AD4008
are shown in Figure 32 and Table 9.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT
+FSR – 1.5 LSB
+FSR – 1 LSB
–FSR + 1 LSB
–FSR
–FSR + 0.5 LSB
Figure 32. ADC Ideal Transfer Function (FSR Is Full-Scale Range)
Table 9. Output Codes and Ideal Input Voltages
Description
Analog Input, VREF = 5 V
VREF = 5 V with Span Compression Enabled (V)
Digital Output Code
FSR − 1 LSB
4.999924 V
4.499939
0xFFFF1
Midscale + 1 LSB
2.500076 V
2.500061
0x8001
Midscale
2.5 V
2.5
0x8000
Midscale − 1 LSB
2.499924 V
2.499939
0x7FFF
−FSR + 1 LSB
76.3 µV
0.50006103
0x0001
−FSR
0 V
0.5
0x00002
1
This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with span compression disabled and above 0.9 × VREF with span compression
enabled).
2
This output code is also the code for an underranged analog input (VIN+ − VIN− below 0 V with span compression disabled and below 0.1 × VREF with span compression
enabled).


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