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LTC3832EGN Datasheet(PDF) 11 Page - Linear Technology |
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LTC3832EGN Datasheet(HTML) 11 Page - Linear Technology |
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11 / 24 page  11 LTC3832/LTC3832-1 sn3832 3832fs Connecting a 82k resistor from FREQSET to ground forces 15 µA out of the pin, causing the internal oscillator to run at approximately 450kHz. Forcing an external 20 µA current into FREQSET cuts the internal frequency to 100kHz. An internal clamp prevents the oscillator from running slower than about 50kHz. Tying FREQSET to VCC forces the chip to run at this minimum speed. The LTC3832-1 does not have this frequency adjustment function. Shutdown The LTC3832 includes a low power shutdown mode, controlled by the logic at the SHDN pin. A high at SHDN allows the part to operate normally. A low level at SHDN for more than 100 µs forces the LTC3832 into shutdown mode. In this mode, all internal switching stops, the COMP and SS pins pull to ground and Q1 and Q2 turn off. The LTC3832 supply current drops to <10 µA, although off- state leakage in the external MOSFETs may cause the total VIN current to be some what higher, especially at elevated temperatures. If SHDN returns high, the LTC3832 reruns a soft-start cycle and resumes normal operation. The LTC3832-1 does not have this shutdown function. External Clock Synchronization The LTC3832 SHDN pin doubles as an external clock input for applications that require a synchronized clock. An internal circuit forces the LTC3832 into external synchronization mode if a negative transition at the SHDN pin is detected. In this mode, every negative transition on the SHDN pin resets the internal oscillator and pulls the ramp signal low, this forces the LTC3832 internal oscil- lator to lock to the external clock frequency. The LTC3832-1 does not have this external synchronization function. The LTC3832 internal oscillator can be externally synchro- nized from 100kHz to 500kHz. Frequencies above 300kHz can cause a decrease in the maximum obtainable duty cycle as rise/fall time and propagation delay take up a larger percentage of the switch cycle. Circuits using these frequencies should be checked carefully in applications where operation near dropout is important—like 3.3V to 2.5V converters. The low period of this clock signal must not be >100 µs, or else the LTC3832 enters shutdown mode. Figure 5 describes the operation of the conventional synchronization function. A negative transition at the SHDN pin forces the internal ramp signal low to restart a new PWM cycle. Notice that the ramp amplitude is lowered as the external clock frequency goes higher. The effect of this decrease in ramp amplitude increases the open-loop gain of the controller feedback loop. As a result, the loop crossover frequency increases and it may cause the feed- back loop to be unstable if the phase margin is insufficient. To overcome this problem, the LTC3832 monitors the peak voltage of the ramp signal and adjusts the oscillator charging current to maintain a constant ramp peak. APPLICATIO S I FOR ATIO SHDN 300kHz FREE RUNNING RAMP SIGNAL TRADITIONAL SYNC METHOD WITH EARLY RAMP TERMINATION LTC3832 KEEPS RAMP AMPLITUDE CONSTANT UNDER SYNC RAMP SIGNAL WITH EXT SYNC RAMP AMPLITUDE ADJUSTED 3832 F05 Figure 5. External Synchronization Operation Input Supply Considerations/Charge Pump The LTC3832 requires four supply voltages to operate: VIN for the main power input, PVCC1 and PVCC2 for MOSFET gate drive and a clean, low ripple VCC for the LTC3832 internal circuitry (Figure 6). The LTC3832-1 has the PVCC2 and VCC pins tied together inside the package (Figure 7). This pin, brought out as VCC/PVCC2, has the same low ripple requirements as the LTC3832, but must also be able to supply the gate drive current to Q2. |
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