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LTC3408 Datasheet(PDF) 11 Page - Linear Technology |
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LTC3408 Datasheet(HTML) 11 Page - Linear Technology |
11 / 12 page 11 LTC3408 3408f dissipate (0.531A)2 • 0.08 Ω = 22.6mW. Thus, TJ = 70°C + (0.0143 + 0.0425)(43) = 71.1 °C. Reductions in power dissipation occur at higher supply voltages, where the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ILOAD • ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or dis- charge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability prob- lem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1 µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10 µF capacitor charging to 3.3V would require a 250 µs rise time, limiting the charging current to about 130mA. APPLICATIO S I FOR ATIO Figure 6. Suggested Layout Figure 5. Layout Diagram VOUT REF RUN 1 2 3 4 8 7 6 5 LTC3408 3403 F05 VIN VOUT CIN VOUT SW GND DAC RREF CREF COUT BOLD LINES INDICATE HIGH CURRENT PATHS VIN VIN 8 7 6 5 1 2 3 4 VOUT VIN REF RUN VOUT VIN GND SW RREF CREF L1 COUT CIN LTC3408 TO DAC VIA TO REF VIA TO PIN 8 VIA TO PIN 7 VIA TO GND VIA TO PIN 1 VIA TO VIN 3408 F06 VIA TO PIN 2 PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3408. These items are also illustrated graphically in Figures 5 and 6. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace and the VIN traceshouldbekeptshort,directandwide. 2. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC drive to the internal power MOSFETs. 3. Keep the (–) plates of CIN and COUT as close as possible. Design Example As a design example, assume the LTC3408 is used in a single lithium-ion battery-powered cellular phone applica- tion. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 0.6A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 2.5V. With this information we can calculate L using Equation (1), L fI V V V L OUT OUT IN = ∆ 1 1 ()( ) – (2) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. |
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