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ECT25S80LM1CR Datasheet(PDF) 4 Page - E-CMOS Corporation |
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ECT25S80LM1CR Datasheet(HTML) 4 Page - E-CMOS Corporation |
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4 / 45 page  E-CMOS Corp. (www.ecmos.com.tw) Page 4 of 45 5B16N-Rev.F001 ECT25S80 8M BIT SPI NOR FLASH Serial Clock (SCLK) This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data Input are latched on the rising edge of the SCLK signal. Data output changes after the falling edge of SCLK. Serial Input (SI)/IO0 This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed. Values are latched on the rising edge of serial SCK clock signal. SI becomes IO0 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). Serial Data Output (SO)/IO1 This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock signal. SO becomes IO1 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). Write Protect (/WP)/IO2 When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1andSRP0) of the status Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the status Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the memory area that are protected by the Block Protect, TB, SEC, and CMP bits in the status registers, are also hardware protected against data modification while /WP remains Low. The /WP function is not available when the Quad mode is enabled (QE) in Status Register 2 (SR2[1]=1). The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK). /WP has an internal pull-up resistance; when unconnected; /WP is at VIH and may be left unconnected in the host system if not used for Quad mode. HOLD (/HOLD)/IO3 The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the operation of wire staus register, programming, or erasing in progress. The operation of HOLD,need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK signal being low(if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The Hold condition starts on the falling edge of the Hold (/HOLD) signal, provided that this coincides with SCK being at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic low state, the Hold condition starts whenever the SCK signal reaches the logic low state.Taking the /HOLD signal to the logic low state does not terminate any Write, Program or Erase operation that is currently in progress. VCC Power Supply |
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