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ECT25S80SM1CR Datasheet(PDF) 8 Page - E-CMOS Corporation |
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ECT25S80SM1CR Datasheet(HTML) 8 Page - E-CMOS Corporation |
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8 / 45 page  E-CMOS Corp. (www.ecmos.com.tw) Page 8 of 45 5B16N-Rev.F001 ECT25S80 8M BIT SPI NOR FLASH Erase/Program Suspend status. Table 3. Status Register-2 (SR2) Table 4. Status Register-1 (SR1) BIT Name Function Default Value Description 7 SUS Suspend Status 0 0 = Erase/Program not suspended 1 = Erase/Program suspended 6 CMP Complement Protect 0 0 = Normal Protection Map 1 = Inverted Protection Map 5 LB3 Security Register Lock Bits 0 OTP Lock Bits 3:1 for Security Registers 3:1 0 = Security Register not protected 1 = Security Register protected 4 LB2 0 3 LB1 0 2 Reserved Reserved 0 1 QE Quad Enable 0 0 = Quad Mode Not Enabled, the /WP pin and /HOLD are enabled. 1 = Quad Mode Enabled, the IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled 0 SRP1 Status Resister Protect 1 0 0 = SRP0 selects whether /WP input has effect on protection of the status register 1 = SRP0 selects Power Supply Lock Down or OTP Lock Down mode BIT Name Function Default Value Description 7 SRP0 Status Resister Protect 0 0 0 = /WP input has no effect or Power Supply Lock Down mode 1 = /WP input can protect the Status Register or OTP Lock Down 6 SEC Sector/Block Protect 0 0 = BP2-BP0 protect 64KB blocks 1 = BP2-BP0 protect 4KB sectors 5 TB Top/Bottom Protect 0 0 = BP2-BP0 protect from the Top down 1 = BP2-BP0 protect from the Bottom up 4 BP2 Block Protect Bits 0 000b = No protection See Table 6 and Table 7 for protection ranges 3 BP1 0 2 BP0 0 1 WEL Write Enable Latch 0 0 = Not Write Enabled, no embedded operation can start 1 = Write Enabled, embedded operation can start 0 WIP Write in Progress Status 0 0 = Not Busy, no embedded operation in progress 1 = Busy, embedded operation in progress |
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