VDD

VG

VS

VD

REG

10

UCC24612

SLUSCM5 – AUGUST 2017

www.ti.com

Submit Documentation Feedback

Copyright © 2017, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Power Management

The UCC24612 synchronous-rectifier (SR) controller is powered from REG pin through the internal linear

regulator between VDD pin and REG pin. This configuration allows optimal design the gate driver stage to

achieve fast driving speed, low driving loss and higher noise immunity.

In low side configuration, as shown in Figure 5, the UCC24612 is powered from the output voltage directly.

Figure 5. UCC24612 Used in Low Side SR Configuration

During start up, the output voltage rises from 0 V. With the rising of output voltage, the internal linear regulator

operates in a passthrough mode, and the REG pin voltage rises together with the output voltage. The UVLO

function of UCC24612 monitors the voltage on REG pin instead of VDD pin. Before REG pin voltage becomes

rises above the UVLO on threshold, the device starts to consume the full operating current and controls the on

and off the SR MOSFETs.

When VDD voltage is above ~9.5 V, the internal linear regulator operates in regulator mode. The REG pin is well

regulated at 9.5 V. This allows the optimal driving voltage for the SR MOSFET without increasing the gate driver

loss. The internal regulator is rated at 10 mA of load regulation capability for higher switching frequency

operation. It is required to have sufficient bypass capacitor on REG pin to ensure stable operation of the linear

regulator. A 2.2 µF bypass capacitor is recommended.

When VDD voltage is below 9.5 V, the internal linear regulator operates in passthrough mode. Depending on the

load current, the regulator has a voltage drop approximately 0.2 V. The UCC24612 continue operates during this

mode until the REG pin voltage drops below UVLO turn off level.

A typical time diagram of VDD and REG pin voltage can be found in Figure 6