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LMR33630 Datasheet(PDF) 10 Page - Texas Instruments |
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LMR33630 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 33 page VOUT PG High = Power Good Low = Fault (95%) (93%) (107%) (105%) VPG-HIGH_UP VPG-HIGH-DN VPG-LOW-UP VPG-LOW-DN 10 LMR33630 SNVSAN3 – AUGUST 2017 www.ti.com Product Folder Links: LMR33630 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Feature Description (continued) The power-good output consists of an open drain NMOS; requiring an external pull up resistor to a suitable logic supply. It can also be pulled up to either VCC or VOUT, through an appropriate resistor, as desired. If this function is not needed, the PG pin should be grounded. When EN is pulled low, the flag output is also forced low. With EN low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤ 4 mA. Figure 7. Static Power-Good Operation |
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