EC24C1024A

1024K bits Two-wire Serial EEPROM

Page 5 of 14

5B13N-Rev.F001

Write Operation

Access each data in the memory requires a 17-bit

address.(The most significant bit A[16] is in the device

address and the Least significant bits A[15]~A[0] are

defined in two address bytes).The most significant word

address followed by the least significant word address.

Byte Write

In the Byte Write mode, the Master device sends the

Start condition and the Slave address information (with

the R/W set to Zero) to the Slave device. After the Slave

generates an ACK, the Master sends the byte address

that is to be written into the address pointer of the

EC24C1024A. After receiving another ACK from the

Slave, the Master device transmits the data byte to be

written

into

the

address

memory

location.

The

EC24C1024A acknowledges once more and the Master

generates the Stop condition, at which time the device

begins its internal programming cycle. While this internal

cycle is in progress, the device will not respond to any

request from the Master device.

Page Write

The EC24C1024A is capable of 256-byte Page-Write

operation. A Page-Write is initiated in the same manner

as a Byte Write, but instead of terminating the internal

Write cycle after the first data word is transferred, the

Master device can transmit up to 255 more bytes. After

the receipt of each data word, the EEPROM responds

immediately with an ACK on SDA line, and the seven

lower order data word address bits are internally

incremented by one, while the higher order bits of the

data word address remain constant. If a byte address is

incremented from the last byte of a page, it returns to the

first byte of that page. If the Master device should

transmit more than 256 bytes prior to issuing the Stop

condition, the address counter will “roll over,” and the

previously written data will be overwritten. Once all 256

bytes are received and the Stop condition has been sent

by the Master, the internal programming cycle begins. At

this point, all received data is written to the EC24C1024A

in a single Write cycle. All inputs are disabled until

completion of the internal Write cycle.

Acknowledge (ACK) Polling

The disabling of the inputs can be used to take

advantage of the typical Write cycle time. Once the Stop

condition is issued to indicate the end of the host's Write

operation, the EC24C1024A initiates the internal Write

cycle. ACK polling can be initiated immediately. This

involves issuing the Start condition followed by the Slave

address for a Write operation. If the EEPROM is still busy

with the Write operation, no ACK will be returned. If the

EC24C1024A has completed the Write operation, an

ACK will be returned and the host can then proceed with

the next Read or Write operation.

Read Operation

Read operations are initiated in the same manner as

Write operations, except that the (R/W) bit of the Slave

address is

set to “1”. There are three Read operation

options: current address read, random address read and

sequential read.

Current Address Read

The EC24C1024A contains an internal address counter

which maintains the address of the last byte accessed,

incremented by one. For example, if the previous

operation is either a Read or Write operation addressed

to the address location n, the internal address counter

would increment to address location n+1. When the

EEPROM receives the Slave Addressing Byte with a

Read operation

(R/W bit set to “1”), it will respond an

ACK and transmit the 8-bit data byte stored at address

location n+1. The Master should not acknowledge the

transfer but should generate a Stop condition so the

EC24C1024A discontinues transmission. If 'n' is the last

byte of the memory, the data from location '0' will be

transmitted. (Refer to Figure 8. Current Address Read

Diagram.)

Random Address Read

Selective Read operations allow the Master device to

select at random any memory location for a Read

operation. The Master device first performs a 'dummy'

Write operation by sending the Start condition, Slave

address and byte address of the location it wishes to

read. After the EC24C1024A acknowledges the byte

address, the Master device resends the Start condition

and the Slave address, this time with the R/W bit set to

one. The EEPROM then responds with its ACK and

sends the data requested. The Master device does not

send an ACK but will generate a Stop condition. (Refer to