CY62128DV30
MoBL
Document #: 38-05231 Rev. *C
Page 5 of 11
Switching Characteristics (Over the Operating Range)[8]
Parameter
Description
CY62128DV30-55
CY62128DV30-70
Unit
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55
70
ns
tAA
Address to Data Valid
55
70
ns
tOHA
Data Hold from Address Change
10
10
ns
tACE
CE1 LOW or CE2 HIGH to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low Z[9]
55
ns
tHZOE
OE HIGH to High Z[9,10]
20
25
ns
tLZCE
CE1 LOW or CE2 HIGH to Low Z
[9]
10
10
ns
tHZCE
CE1 HIGH or CE2 LOW to High Z
[9,10]
20
25
ns
tPU
CE1 LOW or CE2 HIGH to Power-up
0
0
ns
tPD
CE1 HIGH or CE2 LOW to Power-down
55
70
ns
Write Cycle[11]
tWC
Write Cycle Time
55
70
ns
tSCE
CE1 LOW or CE2 HIGH to Write End
40
60
ns
tAW
Address Set-up to Write End
40
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
50
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High Z[9,10]
20
25
ns
tLZWE
WE HIGH to Low Z[9]
10
10
ns
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
Notes:
8.
Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of
the specified IOL.
9.
At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t.
10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals.
12. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
13. WE is HIGH for Read cycle.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
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