512K x 8 PDIP Static RAM
CYM1465A
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05269 Rev. **
Revised March 15, 2002
65A
Features
• 4.5V–5.5V operation
• CMOS SRAM for optimum speed and power
• Low active power (165 mW max.)
• Low standby power (L Version)—(110
µW max)
• 2V data retention (L Version)
• JEDEC-compatible pinout
• 32-pin, 0.6-inch-wide DIP package
• TTL-compatible inputs and outputs
Functional Description
The CYM1465A is a high-performance CMOS static RAM or-
ganized as 512K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
Output Enable (OE), and three-state drivers. This device has
an automatic power-down feature that reduces power con-
sumption by more than 99% when deselected.
Writing to the SRAM is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
eight input/output pins (I/O0 through I/O7) of the device is then
written into the memory location specified on the address pins
(A0 through A18). Reading from the device is accomplished by
taking chip select (CE) and output enable (OE) LOW while
write enable (WE) remains inactive or HIGH. Under these con-
ditions, the contents of the memory location specified on the
address pins (A0 through A18) will appear on the eight appro-
priate data input/output pins (I/O0 through I/O7).The eight in-
put/output pins (I/O0 through I/O7) are placed in a high imped-
ance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CYM1465A is available in a 32-pin 600-mil wide body
PDIP package.
Selection Guide
CYM1465A-70
CYM1465A-85
Maximum Access Time (ns)
70
85
Maximum Operating Current (mA)
20
20
Maximum Standby Current (
µA)
20
20
Logic Block Diagram
Pin Configuration
Top View
DIP
25
26
27
28
29
30
31
32
23
24
21
22
19
20
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A1
A4
A5
A6
A7
A12
A14
A16
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512 x 256 x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
CE
A17
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