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CY62128DV30
MoBL
Document #: 38-05231 Rev. *C
Page 6 of 11
Read Cycle No. 2 (OE Controlled)[10, 13, 14]
Write Cycle No. 1 (WE Controlled) [11, 15, 16, 17]
Notes:
14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
15. Data I/O is high-impedance if OE = VIH.
16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
t
LZCE
tPU
HIGH IMPEDANCE
t
HZOE
tHZCE
t
PD
HIGH
OE
CE1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
tWC
DATA VALID
t
AW
tSA
tPWE
t
HA
tHD
tSD
tSCE
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O