CY7C1370CV25
CY7C1372CV25
Document #: 38-05235 Rev. *C
Page 6 of 27
Pin Definitions
Name
I/O Type
Pin Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK.
BWa, BWb
BWc, BWd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls
DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd.
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access. After
being deselected, ADV/LD should be driven LOW in order to load a new address.
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
CE3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
OE
Input-
Asynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first clock
when emerging from a deselected state and when the device has been deselected.
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to extend the previous cycle when
required.
DQa
DQb
DQc
DQd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A[17:0] during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a
three-state condition. The outputs are automatically three-stated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE.
DQPa, DQPb
DQPc, DQPd
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0].
During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc
is controlled by BWc, and DQPd is controlled by BWd.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge
of TCK.
TCK
JTAG-Clock
Clock input to the JTAG circuitry.
VDD
Power Supply
Power supply inputs to the core of the device.
VDDQ
I/O Power Supply Power supply for the I/O circuitry.
VSS
Ground
Ground for the device. Should be connected to ground of the system.
NC
–
No connects. This pin is not connected to the die.
NC / VDD
–
Can either be left unconnected or connected to VDD. Must not be connected to VSS.
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