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CY7C66013 Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C66013
Description  Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C66013 Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 8 of 58
2.8
Interrupts
The microcontroller supports eleven maskable interrupts in the vectored interrupt controller. Interrupt sources include the 128-
µs
(bit 6) and 1.024-ms (bit 9) outputs from the free-running timer, five USB endpoints, the USB hub, the DAC port, the GPIO ports,
and the I2C-compatible master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles from LOW ‘0’
to HIGH ‘1.’ The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller
sends a packet to the USB host. The DAC ports have an additional level of masking that allows the user to select which DAC
inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO
interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC
port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can
be rising edge (‘0’ to ‘1’) or falling edge (‘1’ to ‘0’).
2.9
USB
The CY7C66013 and CY7C66113 include an integrated USB Serial Interface Engine (SIE) that supports the integrated periph-
erals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the
hub (two endpoints) and a device address for a compound device (three endpoints). The SIE allows the USB host to communicate
with the hub and functions integrated into the microcontroller. The part includes a 1:4 hub repeater with one upstream port and
four downstream ports. The USB Hub allows power-management control of the downstream ports by using GPIO pins assigned
by the user firmware. The user has the option of ganging the downstream ports together with a single pair of power-management
pins, or providing power management for each port with four pairs of power-management pins.


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