Table of Contents

1.0 General Description ..................................................................................................................................... 1

2.0 Features ....................................................................................................................................................... 1

3.0 Block Diagram .............................................................................................................................................. 2

4.0 Ordering Information .................................................................................................................................... 2

5.0 Connection Diagrams ................................................................................................................................... 6

6.0 Architectural Overview ................................................................................................................................. 8

6.1 EMI REDUCTION ...................................................................................................................................... 8

6.2 IN-SYSTEM PROGRAMMING .................................................................................................................. 8

6.3 TRUE IN-SYSTEM EMULATION .............................................................................................................. 8

6.4 ARCHITECTURE

..................................................................................................................................... 8

6.5 INSTRUCTION SET

................................................................................................................................. 8

6.5.1 Key Instruction Set Features ............................................................................................................... 8

6.5.2 Single Byte/Single Cycle Code Execution

......................................................................................... 8

6.5.3 Many Single-Byte, Multi-Function Instructions .................................................................................... 8

6.5.4 Bit-Level Control .................................................................................................................................. 8

6.5.5 Register Set ......................................................................................................................................... 9

6.6 PACKAGING/PIN EFFICIENCY ................................................................................................................ 9

7.0 Absolute Maximum Ratings ....................................................................................................................... 10

8.0 Electrical Characteristics ............................................................................................................................ 10

9.0 Pin Descriptions ......................................................................................................................................... 13

9.1 EMULATION CONNECTION ................................................................................................................... 15

10.0 Functional Description .............................................................................................................................. 15

10.1 CPU REGISTERS ................................................................................................................................. 15

10.2 PROGRAM MEMORY ........................................................................................................................... 16

10.3 DATA MEMORY .................................................................................................................................... 16

10.4 OPTION REGISTER ............................................................................................................................. 16

10.5 SECURITY ............................................................................................................................................ 17

10.6 RESET ................................................................................................................................................... 17

10.6.1 External Reset ................................................................................................................................. 18

10.6.2 On-Chip Power-On Reset ................................................................................................................ 18

10.7 OSCILLATOR CIRCUITS ...................................................................................................................... 18

10.7.1 R/C Oscillator ................................................................................................................................... 19

10.7.2 Crystal Oscillator .............................................................................................................................. 20

10.7.3 External Oscillator ............................................................................................................................ 20

10.7.4 Clock Prescaler ................................................................................................................................ 20

10.8 CONTROL REGISTERS ....................................................................................................................... 20

10.8.1 CNTRL Register (Address X'00EE) ................................................................................................. 20

10.8.2 PSW Register (Address X'00EF) ..................................................................................................... 20

10.8.3 ICNTRL Register (Address X'00E8) ................................................................................................ 21

10.8.4 ITMR Register (Address X'00CF) .................................................................................................... 21

11.0 In-System Programming ........................................................................................................................... 21

11.1 INTRODUCTION ................................................................................................................................... 21

11.2 FUNCTIONAL DESCRIPTION .............................................................................................................. 21

11.3 REGISTERS .......................................................................................................................................... 21

11.3.1 ISP Address Registers ..................................................................................................................... 21

11.3.2 ISP Read Data Register .................................................................................................................. 22

11.3.3 ISP Write Data Register ................................................................................................................... 22

11.3.4 ISP Write Timing Register ................................................................................................................ 22

11.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM ..................... 23

11.5 FORCED EXECUTION FROM BOOT ROM ......................................................................................... 23

11.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET ....................................................... 23

11.7 MICROWIRE/PLUS ISP ........................................................................................................................ 23

12.0 Timers ....................................................................................................................................................... 25

12.1 TIMER T0 (IDLE TIMER) ...................................................................................................................... 25

12.1.1 ITMR Register .................................................................................................................................. 25

12.2 TIMER T1 .............................................................................................................................................. 26

12.3 MODE 1. PROCESSOR INDEPENDENT PWM MODE ....................................................................... 26

12.4 MODE 2. EXTERNAL EVENT COUNTER MODE ................................................................................ 26

12.5 MODE 3. INPUT CAPTURE MODE ..................................................................................................... 27

12.6 TIMER CONTROL FLAGS .................................................................................................................... 28

13.0 Power Save Modes .................................................................................................................................. 28

13.1 HALT MODE .......................................................................................................................................... 28

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