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EC3292 Datasheet(PDF) 8 Page - E-CMOS Corporation |
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EC3292 Datasheet(HTML) 8 Page - E-CMOS Corporation |
8 / 10 page 2A, 18V, Synchronous Step-down DC/DC Converter EC3292 E-CMOS Corp. (www.ecmos.com.tw) Page 8 of 10 3L03N-Rev.P001 can be optimized for a wide range of capacitance and ESR values. Compensation Components EC3292 employs current mode control for easy compensation and fast transient response. The system stability and transient response are controlled through the COMP pin. COMP pin is the output of the internal transconductance error amplifier. A series capacitor and resistor combination sets a pole-zero combination to control the characteristics of the control system. The DC gain of the voltage feedback loop is given by: AVDC = RLOAD × GCS × AEA × VFB/VOUT Where AEA is the error amplifier voltage gain; GCS is the current sense transconductance and RLOAD is the load resistor value. The system has two poles of importance. One is due to the compensation capacitor (C3) and the output resistor of the error amplifier, and the other is due to the output capacitor and the load resistor. These poles are located at: fP1 = GEA / (2π × C3 × AEA) fP2 = 1 / (2π × C2 × RLOAD) Where GEA is the error amplifier transconductance. The system has one zero of importance, due to the compensation capacitor (C3) and the compensation resistor (R3). This zero is located at: fZ1 = 1 / (2π × C3 × R3) The system may have another zero of importance, if the output capacitor has a large capacitance and/or a high ESR value. The zero, due to the ESR and capacitance of the output capacitor, is located at: fESR = 1 / (2π × C2 × RESR) In this case, a third pole set by the compensation capacitor (C6) and the compensation resistor (R3) is used to compensate the effect of the ESR zero on the loop gain. This pole is located at: fP3 = 1 / (2π × C6 × R3) The goal of compensation design is to shape the converter transfer function to get a desired loop gain. The system crossover frequency where the feedback loop has the unity gain is important. Lower crossover frequencies result in slower line and load transient responses, while higher crossover frequencies could cause system instability. A good rule of thumb is to set the crossover frequency below one-tenth of the switching frequency. To optimize the compensation components, the following procedure can be used. 1. Choose the compensation resistor (R3) to set the desired crossover frequency. Determine the R3 value by the following equation: R3 = [ (2π × C2 × f C) / (GEA × GCS) ] × (VOUT/VFB) < [ (2π × C2 × 0.1 × f S) / (GEA × GCS) ] × (VOUT/VFB) Where fC is the desired crossover frequency which is typically below one tenth of the switching frequency. 2. Choose the compensation capacitor (C3) to achieve the desired phase margin. For applications with typical inductor values, setting the compensation zero, fZ1, below one-forth of the crossover frequency provides sufficient phase margin. Determine the C3 value by the following equation: C3 > 4 / (2π × R3 × f C) Where R3 is the compensation resistor. 3. Determine if the second compensation capacitor (C6) is required. It is required if the ESR zero of the output capacitor is located at less than half of the switching frequency, or the following relationship is valid: 1 / (2π × C2 × R ESR) < fS/2 If this is the case, then add the second compensation capacitor (C6) to set the pole fP3 at the location of the ESR zero. Determine the C6 value by the equation: C6 = (C2 × RESR) / R3 |
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