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AT75C310 Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT75C310 Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 17 page  AT75C310 4 Figure 3. DRAM Read Cycle (Burst Read) Table 2. DRAM Read Cycle (Burst Read) Timings Symbol Parameter Min (ns) Max (ns) t CPRH RAS Hold Time from CAS Precharge 48.0 – tCSH CAS Hold Time 61.0 – t RCD RAS to CAS Delay Time 41.0 – t CAS CAS Pulse Width 20.0 – tCP CAS Precharge Time 19.0 – t ASR Row Address Setup Time 1.5 t RAH Row Address Hold Time 22.0 tASC Column Address Setup Time 15.0 t CAH Column Address Hold Time 21.0 t CAC Access Time from CAS – 22.0 tOEA Access Time from NDOE – 34.0 t AA Access Time from Column Address – 38.0 t RAC Access Time from RAS – 63.0 tCPA Access Time from CAS Precharge – 43.0 t OHO Data Hold from NDOE 0 – t DOH Data Hold from CAS Low 0 – tAA tRAC tOEA tCAC tRCD tCSH tCPRH tCAS tCAH tASC tRAH tASR D NDOE A NCASx NRASx tCAS tCP tCAH tASC tCAC tAA tDOH tCPA tOHO |
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