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ADC32RF82 Datasheet(PDF) 56 Page - Texas Instruments |
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ADC32RF82 Datasheet(HTML) 56 Page - Texas Instruments |
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56 / 151 page  56 ADC32RF82 SBAS869 – SEPTEMBER 2017 www.ti.com Product Folder Links: ADC32RF82 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 8.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output Table 16 lists the available JESD204B formats and valid ranges for the ADC32RF82 with decimation (single- band DDC) when using real output format. The ranges are limited by the SerDes line rate and the maximum ADC sample frequency. Table 17 shows the sample alignment on the different lanes. Table 16. JESD Mode Options: Single-Band Real Output (Wide Bandwidth) DECIMATION SETTING (Complex) NUMBER OF ACTIVE DDCS L M F S PLL MODE JESD MODE0 JESD MODE1 JESD MODE2 RATIO [fSerDes / fCLK (Gbps / GSPS)] Divide-by-4 (Divide-by-2 real) 1 per channel 8 2 2 4 20x 1 0 0 2.5 4 2 4 4 40x 2 0 0 5 4 2 1 1 40x 0 0 1 Divide-by-6 (Divide-by-3 real) 1 per channel 8 2 2 4 20x 1 0 0 1.67 4 2 4 4 40x 2 0 0 3.33 4 2 1 1 40x 0 0 1 Table 17. JESD Sample Lane Alignment: Single-Band Real Output (Wide Bandwidth) OUTPUT LANE LMFS = 8224 LMFS = 4244 LMFS = 4211 DA0 A0[15:8] A0[7:0] DA1 A1[15:8] A1[7:0] A0[15:8] A0[7:0] A1[15:8] A1[7:0] A0[15:8] DA2 A2[15:8] A2[7:0] A2[15:8] A2[7:0] A3[15:8] A3[7:0] A0[7:0] DA3 A3[15:8] A3[7:0] DB0 B0[15:8] B0[7:0] DB1 B1[15:8] B1[7:0] B0[15:8] B0[7:0] B1[15:8] B1[7:0] B0[15:8] DB2 B2[15:8] B2[7:0] B0[15:8] B2[7:0] B3[15:8] B3[7:0] B0[7:0] DB3 B3[15:8] B3[7:0] |
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