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A8237 Datasheet(PDF) 2 Page - Altera Corporation

Part No. A8237
Description  PROGRAMMABLE DMA CONTROLLER
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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Altera Corporation
a8237 Programmable DMA Controller Data Sheet
Table 1 describes the input and output ports of the a8237 MegaCore
function.
Table 1. a8237 Ports (Part 1 of 2)
Name
Type
Polarity
Description
clk
Input
Clock. Used to generate and synchronize a8237 operations.
hlda
Input
High
Hold acknowledge. This signal from the microprocessor indicates the
release of the system bus to the a8237.
ncs
Input
Low
Chip select. When ncs is active, the a8237 is selected, and read and
write transactions to internal registers are enabled.
neopin
Input
Low
End of process. Permits external termination of the current DMA service.
niorin
Input
Low
I/O read control. When niorin is low and the a8237 is selected, read
transactions from internal registers are enabled.
niowin
Input
Low
I/O write control. When niowin is low and the a8237 is selected, data is
asynchronously written into the a8237.
ready
Input
High
Ready. Extends the read and write pulses associated with slow memory
or peripherals. When ready is low, wait states are inserted until ready
returns high.
reset
Input
High
Reset. Clears the command, status, request, and temporary registers.
Also clears the byte pointer, mode register counter, and the controller
state machine. Sets the mask register so requests are ignored after
initialization.
ain[3..0]
Input
Register address bus. Selects one of the internal a8237 registers. See
Table 2 on page 9.
dbin[7..0]
Input
Data bus input. The microprocessor writes data to internal registers via
the dbin[7..0] bus.
dreq[3..0]
Input
DMA request bus. Programmable polarity. Asynchronous signals from
peripherals requesting DMA service.
adstb
Output
High
Address strobe. Latches the MSB of the DMA address from
dbout[7..0]
into an external address latch.
aen
Output
High
Address enable. Enables an external address latch containing the most
significant address byte of a DMA transfer.
dben
Output
High
Data bus enable. Active when data registers are read. Also active during
DMA transfers, allowing the most significant bit (MSB) of the address to
latch the output of temporary register data during memory-to-memory
writes.
dmaenable
Output
High
DMA enable. Asserted during an active DMA cycle. Can create
bidirectional signals from the niorin, niorout, niowin, and niowout
signals, and the lower four bits of the address bus.
hrq
Output
High
Hold request. Requests control of the system bus.
neopout
Output
Low
End of process. Indicates normal termination of a DMA transfer.
niorout
Output
Low
I/O read output. Read strobe to I/O devices as DMA writes to memory.




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