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TLV320AIC26 Datasheet(PDF) 6 Page - Texas Instruments

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Part No. TLV320AIC26
Description  LOW POWER STEREO AUDIO CODEC WITH HEADPHONE/SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

TLV320AIC26 Datasheet(HTML) 6 Page - Texas Instruments

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TLV320AIC26
SLAS412− DECEMBER 2003
www.ti.com
6
ELECTRICAL CHARACTERISTICS
At +25
°C, AVDD,DRVDD,IOVDD = 3.3 V, DVDD = 1.8 V, Int. Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE REFERENCE
Voltage range
VREF output programmed as 2.5 V
2.3
2.5
2.7
V
Voltage range
VREF output programmed as 1.25 V
1.15
1.25
1.35
V
Voltage range
External VREF. By design, not tested in
production.
1.2
2.55
V
Reference drift
Internal VREF = 1.25 V
29
ppm/
°C
Current drain
Extra current drawn when the internal
reference is turned on.
650
µA
DIGITAL INPUT / OUTPUT(1)
Internal clock frequency
8.8
MHz
Logic family
CMOS
Logic level:
VIH
IIH = +5 µA
0.7xIOVDD
V
VIL
IIL = +5 µA
−0.3
0.3xIOVDD
V
VOH
IOH = 2 TTL loads
0.8xIOVDD
V
VOL
IOL = 2 TTL loads
0.1xIOVDD
V
Capacitive load
10
pF
POWER SUPPLY REQUIREMENTS
Power supply voltage
AVDD(2)
2.7
3.6
V
DRVDD(2)
2.7
3.6
V
IOVDD
1.1
3.6
V
DVDD
1.525
1.95
V
IAVDD
48 ksps, output drivers in low
2.2
Stereo audio playback
IDRVDD
48 ksps, output drivers in low
power mode, VGND off, PLL
off
0
mA
Stereo audio playback
IDVDD
power mode, VGND off, PLL
off
2.4
mA
IAVDD
2.9
Microphone record
IDRVDD
48 ksps, no playback, PLL off
0
mA
Microphone record
IDVDD
48 ksps, no playback, PLL off
1.4
mA
IAVDD
Additional power consumed
0.1
PLL
IDRVDD
Additional power consumed
when PLL is enabled.
1.3
mA
PLL
IDVDD
when PLL is enabled.
0.9
mA
IAVDD
Additional power consumed
0.3
VGND
IDRVDD
Additional power consumed
when VGND is powered.
0.9
mA
VGND
IDVDD
when VGND is powered.
0
mA
Hardware power down
All currents
2
µA
(1) Internal oscillator is designed to give nominally 8-MHz clock frequency. However, due to process variations, this frequency can vary from device
to device. All calculations for delays and wait times in the data sheet assume an 8-MHz oscillator clock.
(2) It is recommended that AVDD and DRVDD be set to the same voltage for the best performance. It is also recommended that these supplies be
separated on the user’s PCB.


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