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IC-MD Datasheet(PDF) 5 Page - IC-Haus GmbH |
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IC-MD Datasheet(HTML) 5 Page - IC-Haus GmbH |
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5 / 30 page  preliminary preliminary iC-MD 48-BIT QUADRATURE COUNTER WITH RS422 RECEIVER AND SPI/BISS INTERFACE Rev B1, Page 5/30 ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 3 . . . 5.5 V, Tj = -40 . . . 125 °C, unless otherwise noted. Item Symbol Parameter Conditions Unit No. Min. Typ. Max. General 001 VDD Voltage Supply VDD 3 5.5 V 002 I(VDD) Supply Current in VDD TTL input configuration, 48 bits counter 15 mA 10 MHz signal in AP (0º phase) and AN (90º phase), BP, BN, CP and CN to GND 003 Vc()hi Clamp Voltage hi Vc()hi = V() - VDD, I() = 1 mA, all pins 0.4 1.5 V 004 Vc()lo Clamp Voltage lo Vc()hi = V() - VDD, I() = 1 mA, all pins -1.5 -0.25 V Digital Inputs: MA, SLI, SCK, MOSI, NCS, TPI 101 Vt()hi Input Threshold Voltage hi 2 V 102 Vt()lo Input Threshold Voltage lo VDD = 4.5 . . . 5.5 V 0.8 V VDD = 3 . . . 5.5 V 0.75 V 103 Vt()hys Input Hysteresis 150 250 mV 104 Ipd() Input Pull-down Current at SCK, MOSI, TPI V() = 1 V . . . VDD 2 30 75 µA 105 Ipu() Input Pull-Up Current at NCS, MA V() = 0 V . . . VDD - 1 V -75 -30 -2 µA 106 fclk(MA) Permissible Clock Frequency at MA ENSSI = 1 (SSI protocol) 4 MHz ENSSI = 0 (BiSS protocol) 10 MHz 107 Voc() Pin Open Voltage at SLI 42 46.5 51 %VDD 108 Ri() Internal Resistance at SLI Referenced to VDD 70 170 kΩ Referenced to GND 40 110 kΩ 109 to(SLI) Digital Filter at SLI SLI = open 5 25 µs 110 fclk(SCK) Permissible Clock Frequency at SCK 10 MHz Bidirectional Pins: NWARN, NERR 201 Ipu() Pull-Up Current V() = 0 V . . . VDD - 1 V -850 -100 -10 µA 202 Vt()hi Input Threshold Voltage hi 2 V 203 Vt()lo Input Threshold Voltage lo VDD = 4.5 . . . 5.5 V 0.8 V VDD = 3 . . . 5.5 V 0.75 V 204 Vt()hys Input Hysteresis 150 250 mV 205 Vs()lo Saturation Voltage lo I() = 4 mA 450 mV 206 Isc()lo Short-Circuit Current lo V() = 0 V . . . VDD 4 100 mA ABZ Counter 301 R() Counter Resolution 48 bit 302 fcnt() Permissible Count Frequency 40 MHz 303 PHab2 Permissible A/B Phase Distance edge A vs. edge B and vice versa TTL=1 5 ns TTL=0, LVDS=X 13 ns Power-Down Reset and Oscillator 601 VDDon Power-On Supply Voltage 2.9 V 602 VDDoff Power-Down Voltage 2.1 V 603 VDDhys Power-On Hysteresis VDDon - VDDoff 35 100 mV 604 f(CLK) Internal Oscillator Frequency VDD = 3.5 . . . 5.5 V 1.4 5.6 MHz VDD = 3 . . . 3.5 V 1.6 6.7 MHz Digital Outputs: SLO, MISO, ACT0, ACT1 701 Vs()hi Saturation Voltage hi Vs()hi = VDD - V(), I() = -4 mA 450 mV 702 Vs()lo Saturation Voltage lo I() = 4 mA 450 mV 703 Isc()hi Short-Circuit Current hi V() = 0 . . . VDD -115 mA 704 Isc()lo Short-Circuit Current lo V() = 0 . . . VDD 100 mA |
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