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IC-LFS Datasheet(PDF) 7 Page - IC-Haus GmbH

Part # IC-LFS
Description  32x1 LINEAR IMAGE SENSOR
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Manufacturer  ICHAUS [IC-Haus GmbH]
Direct Link  http://www.ichaus.biz
Logo ICHAUS - IC-Haus GmbH

IC-LFS Datasheet(HTML) 7 Page - IC-Haus GmbH

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iC-LFS
32x1 LINEAR IMAGE SENSOR
Rev A2, Page 7/10
DESCRIPTION OF FUNCTIONS
Normal operation
Following an internal power-on reset the integration
and hold capacitors are discharged and the sample
and hold circuit is set to sample mode. A high signal
at SI and a rising edge at CLK triggers a readout cycle
and with it a new integration cycle.
In this process the hold capacitors of pixels 1 to 31
are switched to hold mode immediately (SNH = 1), with
pixel 32 (SNH32 = 1) following suit one clock pulse later.
This special procedure allows all pixels to be read out
with just 32 clock pulses. The integration capacitors are
discharged by a one clock long reset signal (NRCI = 0)
which occurs between the 2nd and 3rd falling edge of
the readout clock pulse (cf. Figure 4). After the 31 pix-
els have been read out these are again set to sample
mode (SNH = 0), likewise for pixel 32 one clock pulse
later (SNH32 = 0).
SNH
SNH32
NRCI
Integration Time Pixel 1−31
Integration Time Pixel 32
Pix32
Pix31
...
Pix31
Pix32
Pix30
31
Pix1
1
32
3
V(AO)
CLK
SI
Pix2
Pix3
30
1
2
31
32
2
4
...
Pix1
Figure 4: Readout cycle and integration sequence
If prior to the 32th clock pulse a high signal occurs
at SI the present readout is halted and immediately
reinitiated with pixel 1. In this instance the hold ca-
pacitors retain their old value i.e. hold mode prevails
(SNH/SNH32 = 0).
Pix2
Pix3
30
1
32
5
1
Pix4
Pix5
2
3
Pix2
4
Pix32
2
Pix1
...
...
SNH
SNH32
NRCI
2
4
Pix4
Pix3
31
Pix31
Pix32
Pix30
Pix1
Pix1
1
32
3
V(AO)
CLK
SI
Figure 5: Restarting a readout cycle
With more than 32 clock pulses until the next SI signal,
pixel 1 is output without entering hold mode; the out-
put voltage tracks the voltage of the pixel 1 integration
capacitor.


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