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IC-LFM Datasheet(PDF) 6 Page - IC-Haus GmbH

Part No. IC-LFM
Description  64x1 LINEAR IMAGE SENSOR
Download  9 Pages
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Maker  ICHAUS [IC-Haus GmbH]
Homepage  http://www.ichaus.biz
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IC-LFM Datasheet(HTML) 6 Page - IC-Haus GmbH

   
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iC-LFM
64x1 LINEAR IMAGE SENSOR
Rev A1, Page 6/9
DESCRIPTION OF FUNCTIONS
Normal operation
Following an internal power-on reset the integration
and hold capacitors are discharged and the sample
and hold circuit is set to sample mode. A high signal
at SI and a rising edge at CLK triggers a readout cycle
and with it a new integration cycle.
In this process the hold capacitors of pixels 1 to 63
are switched to hold mode immediately (SNH = 1), with
pixel 64 (SNH64 = 1) following suit one clock pulse
later. This special procedure allows all pixels to be
read out with just 64 clock pulses. The integration ca-
pacitors are discharged by a one clock long reset sig-
nal (NRCI = 0) which occurs between the 2nd and 3rd
falling edge of the readout clock pulse (cf. Figure 4).
After the 63 pixels have been read out these are again
set to sample mode (SNH = 0), likewise for pixel 64 one
clock pulse later (SNH64 = 0).
SNH
SNH64
NRCI
Integration Time Pixel 1−63
Integration Time Pixel 64
Pix64
Pix63
...
Pix63
Pix64
Pix62
63
Pix1
1
64
3
V(AO)
CLK
SI
Pix2
Pix3
62
1
2
63
64
2
4
...
Pix1
Figure 4: Readout cycle and integration sequence
If prior to the 64th clock pulse a high signal occurs
at SI the present readout is halted and immediately
re-initiated with pixel 1. In this instance the hold ca-
pacitors retain their old value i.e. hold mode prevails
(SNH/SNH64 = 0).
Pix2
Pix3
62
1
64
5
1
Pix4
Pix5
2
3
Pix2
4
Pix64
2
Pix1
...
...
SNH
SNH64
NRCI
2
4
Pix4
Pix3
63
Pix63
Pix64
Pix62
Pix1
Pix1
1
64
3
V(AO)
CLK
SI
Figure 5: Restarting a readout cycle
With more than 64 clock pulses until the next SI signal,
pixel 1 is output without entering hold mode; the out-
put voltage tracks the voltage of the pixel 1 integration
capacitor.


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