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Z85233 Datasheet(PDF) 75 Page - Zilog, Inc. |
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Z85233 Datasheet(HTML) 75 Page - Zilog, Inc. |
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75 / 317 page  SCC™/ESCC™ User’s Manual SCC/ESCC Ancillary Support Circuitry 3-14 3.6 CRYSTAL OSCILLATOR (Continued) Figure 3-13 shows the use of the DPLL to derive a 1x clock from the data. In this example: The DPLL clock input = BRG output (x16 the data rate) WR14. The DPLL clock output = RxC (receiver clock) WR11. Set FM mode WR14. Set FM mode WR10. 3.6 CRYSTAL OSCILLATOR Each channel contains a high gain oscillator amplifier for use with an external crystal circuit. The amplifier is avail- able between the /RTxC pin (crystal input) and the /SYNC pin (crystal output) for each channel. The oscillator amplifier is enabled by writing WR11 D7=1. While the crystal oscillator is enabled, anything that has selected the /RTxC pin as its clock source automatically connects to the output of the crystal oscillator. Note: The output of the oscillator amplifier can be pro- grammed to output on the /TRxC pin, which is particularly valuable for diagnostic purposes. Because amplifier char- acteristics can be affected by the impedance of measure- ment equipment applied directly to the crystal circuit, using the /TRxC pin allows the oscillation to be tested without af- fecting the circuit. Of course, since the oscillator uses the /RTxC and /SYNC pins, this precludes the use of these pins for other func- tions. In synchronous modes, no sync pulse is output, and the External Sync mode cannot be selected. In asynchro- nous modes, the state of the Sync/Hunt bit in RR0 is no longer controlled by the /SYNC pin. Instead, the Sync/Hunt bit is forced to 0. The crystal oscillator requires some finite time to stabilize and must be allowed to stabilize before it is used as a clock source. This stabilization time is dependent on the external circuit impedance and 20 ms is a suggested minimum. The External Crystal should operate in parallel resonance. For further details on designing with the crystal, refer to Appen- dix A, “On-Chip Oscillator Design”. Figure 3-13. Synchronous Transmission, 1x Clock Rate, FM Data Encoding, using DPLL RxC B R G 16x Data Rate /RTxC Pin /SYNC Pin D P L L TxC RxD Pin RxD External Crystal UM010901-0601 |
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