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Z85233 Datasheet(PDF) 6 Page - Zilog, Inc.

Part No. Z85233
Description  The Zilog SCC Serial Communication Controller
Download  317 Pages
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Maker  ZILOG [Zilog, Inc.]
Homepage  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z85233 Datasheet(HTML) 6 Page - Zilog, Inc.

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SCC™/ESCC™ USERS MANUAL
Chapter 1
Figure 1-1.
SCC Block Diagram .............................................................................................................................. 1-4
Figure 1-2.
Z85X30 Pin Functions .......................................................................................................................... 1-5
Figure 1-3.
Z80X30 Pin Functions .......................................................................................................................... 1-6
Figure 1-4.
Z85X30 DIP Pin Assignments .............................................................................................................. 1-6
Figure 1-5.
Z85X30 PLCC Pin Assignments ........................................................................................................... 1-6
Figure 1-6.
Z80X30 DIP Pin Assignments .............................................................................................................. 1-7
Figure 1-7.
Z80X30 PLCC Pin Assignments ........................................................................................................... 1-7
Chapter 2
Figure 2-1.
Z80X30 Read Cycle ............................................................................................................................. 2-2
Figure 2-2.
Z80X30 Write Cycle .............................................................................................................................. 2-3
Figure 2-3.
Z80X30 Interrupt Acknowledge Cycle .................................................................................................. 2-4
Figure 2-4.
Write Register 7 Prime (WR7') ............................................................................................................. 2-8
Figure 2-5.
Z85X30 Read Cycle Timing ................................................................................................................ 2-10
Figure 2-6.
Z85X30 Write Cycle Timing ................................................................................................................ 2-11
Figure 2-7.
Z85X30 Interrupt Acknowledge Cycle Timing .................................................................................... 2-11
Figure 2-8a.
Write Register 7 Prime (WR7') for the 85230 ..................................................................................... 2-14
Figure 2-8b.
Write Register 7 Prime for the 85C30 ................................................................................................. 2-14
Figure 2-9.
ESCC Interrupt Sources ..................................................................................................................... 2-16
Figure 2-10.
Peripheral Interrupt Structure ............................................................................................................. 2-17
Figure 2-11.
Internal Priority Resolution ................................................................................................................. 2-17
Figure 2-12.
RR3 Interrupt Pending Bits ................................................................................................................. 2-18
Figure 2-13.
Interrupt Flow Chart (for each interrupt source). ................................................................................ 2-20
Figure 2-14.
Write Register 1 Receive Interrupt Mode Control ............................................................................... 2-22
Figure 2-15.
Special Conditions Interrupt Service Flow .......................................................................................... 2-24
Figure 2-16.
Transmit Interrupt Status When WR7' D5=1 For ESCC ..................................................................... 2-26
Figure 2-17.
Transmit Buffer Empty Bit Status For ESCC For Both WR7' and WR7' D5=0 ................................... 2-27
Figure 2-18.
Transmit Interrupt Status When WR7' D5=0 For ESCC ..................................................................... 2-27
Figure 2-19.
TxIP Latching on the ESCC ................................................................................................................ 2-27
Figure 2-20.
Operation of TBE, Tx Underrun/EOM and TxIP on NMOS/CMOS. .................................................... 2-28
Figure 2-21.
Operation of TBE, Tx Underrun/EOM and TxIP on ESCC ................................................................. 2-29
Figure 2-22.
Flowchart example of processing an end of packet ........................................................................... 2-30
Figure 2-23.
RR0 External/Status Interrupt Operation ............................................................................................ 2-31
Figure 2-24.
Wait On Transmit Timing .................................................................................................................... 2-34
Figure 2-25.
Wait On Transmit Timing .................................................................................................................... 2-34
Figure 2-26.
Wait On Receive Timing ..................................................................................................................... 2-35
LIST OF FIGURES
UM010901-0601


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