08 | Keysight | U4164A Logic Analyzer Module - Data Sheet

State mode support for bursty clock inputs allows you to take measurements that include

periods of in activity on the clock, such as power management transitions when the clock is

inactive. In state mode, the U4164A allows one clock input into pod 1 of the clocking module.

– Double module set - bottom module of set is clocking module

– Three card set - middle module is clocking module

There are five clock qualifiers available on the clocking module. The clock inputs to pods 2, 3, 4,

and 5 can be used as “AND” or “OR” clock qualifiers. The “RESET” clock qualifier input on pod

7 is available as an “AND” input only when the other clock qualifiers are setup as “OR” inputs.

The most common use mode for this clock qualifier is to capture “RESET” when the other clock

qualifiers are looking for clock enable (CKE) signals on DDR and LPDDR buses.

Clock hysteresis

The U4164A module has a unique clock hysteresis feature that allows the user to define a range

about the clock threshold. Using clock hysteresis enables the U4164A clock input in state mode

to avoid false sampling on noisy clock inputs that may float to zero volts at the differential

clock input to the U4164A when the clock is turned off. Clock hysteresis improves state mode

captures from systems where a differential clock input turns off and floats to zero volts.

Clock hysteresis control is inside the threshold dialog for the clock. The “hysteresis on” check

box [x] is an on/off control. There is also an input for the amount of hysteresis setting in

millivolts around threshold between 0 and 1 volts.

State Mode Clock Inputs and Clock Qualifiers

Figure 2. Clock hysteresis selection and setting in clock thresholds window. The settings shown were used

to capture an LPDDR4 system initializing without the use of any clock qualifiers.