BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)

S-8224A/B Series

9



Electrical Characteristics

Table 7

(Ta =

+25°C unless otherwise specified)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Test

Circuit

Detection voltage

Overcharge detection voltage n

(n = 1, 2, 3, 4)

Ta =

+25°C

− 0.020

+ 0.020

V

1

Ta =

−10°C to +60°C

*1

− 0.025

+ 0.025

V

1

Overcharge hysteresis voltage n

(n = 1, 2, 3, 4)

× 1.2

× 0.8

V

1

− 0.050

+ 0.050

V

1

−50 mV

− 0.025

+ 0.025

V

1

− 0.025

+ 0.020

V

1

Input voltage

Operation voltage between

VDD pin and VSS pin

−

3.6

−

28

V

−

CTL pin input voltage "H"

−

× 0.95

−

−

V

2

CTL pin input voltage "L"

−

−

−

× 0.4

V

2

Output voltage

CO pin output voltage "H"

S-8224B Series

5.0

8.0

11.5

V

2

Input Current

Current consumption

during operation

V1 = V2 = V3 = V4

− 1.0 V

−

0.25

0.6

μA3

Current consumption

during overdischarge

V1 = V2 = V3 = V4

× 0.5 V

−

−

0.3

μA

3

VC1 pin input current

V1 = V2 = V3 = V4

− 1.0 V

−

−

0.3

μA4

VCn pin input current

(n = 2, 3, 4)

V1 = V2 = V3 = V4

− 1.0 V

−0.3

0

0.3

μA4

CTL pin input current "H"

−

0.6

1.3

2.0

μA

4

CTL pin input current "L"

−

−0.15

−

−

μA

4

Output Current

CO pin source current

S-8224A Series

(CMOS output product),

S-8224B Series

−

−

−20

μA5

CO pin sink current

−

20

−

−

μA5

CO pin leakage current

S-8224A Series

(Nch open-drain output product)

−

−

0.1

μA5

Delay Time

Overcharge detection delay time

−

× 0.8

× 1.2

s

1

Overcharge release delay time

1.6

2.0

3.0

ms

1

51.2

64

76.8

ms

1

−

6

12

20

ms

1

CTL pin response delay time

−

−

−

2.5

ms

2

Transition time to test mode

−

−

−

10

ms

1

*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed

by design, not tested in production.