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S-93C56CD0I-T8T1U3 Datasheet(PDF) 9 Page - Seiko Instruments Inc

Part # S-93C56CD0I-T8T1U3
Description  3-WIRE SERIAL E2PROM
Download  39 Pages
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Manufacturer  SII [Seiko Instruments Inc]
Direct Link  http://www.sii.co.jp
Logo SII - Seiko Instruments Inc

S-93C56CD0I-T8T1U3 Datasheet(HTML) 9 Page - Seiko Instruments Inc

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3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
9
AC Electrical Characteristics
Table 9 Measurement Conditions
Input pulse voltage
0.1
× VCC to 0.9 × VCC
Output reference voltage
0.5
× VCC
Output load
100 pF
Table 10
Item
Symbol
Ta =
−40°C to +85°C
Unit
VCC = 1.6 V to 1.8 V
VCC = 1.8 V to 2.5 V
VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
CS pin setup time
tCSS
0.4
0.2
0.15
0.15
μs
CS pin hold time
tCSH
0
0
0
0
μs
CS pin deselect time tCDS
0.4
0.2
0.2
0.2
μs
Data setup time
tDS
0.2
0.1
0.1
0.1
μs
Data hold time
tDH
0.2
0.1
0.1
0.1
μs
Output delay time
tPD
0.8
0.6
0.25
0.25
μs
Clock frequency
*1
fSK
0
0.5
0
1.0
0
2.0
0
2.0
MHz
SK clock time "L"
*1
tSKL
0.5
0.2
0.2
0.1
μs
SK clock time "H"
*1
tSKH
0.5
0.2
0.2
0.1
μs
Output disable time
tHZ1, tHZ2
0
0.5
0
0.2
0
0.2
0
0.15
μs
Output enable time
tSV
0
0.5
0
0.2
0
0.2
0
0.15
μs
Write time
tPR
4.0
4.0
4.0
4.0
ms
*1.
The clock cycle of the SK clock (frequency fSK) is 1/fSK
μs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1/fSK) = tSKL (min.)
+ tSKH (min.) by minimizing
the SK clock cycle time.
tSKH
tCDS
tCSS
CS
Valid data
Valid data
DI
tSKL
SK
tSV
tHZ2
tCSH
tHZ1
tPD
tPD
tDS tDH
tDS
tDH
High-Z
High-Z
High-Z
DO
DO
(READ)
(VERIFY)
High-Z
*1
1/fSK
*2
*1.
Indicates high impedance.
*2.
1/fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics.
Note that the clock cycle cannot be set as (1/fSK) = tSKL (min.)
+ tSKH (min.) by minimizing the SK clock cycle
time.
Figure 1 Timing Chart


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