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X40626V14I-2.7A Datasheet(PDF) 2 Page - Xicor Inc. |
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X40626V14I-2.7A Datasheet(HTML) 2 Page - Xicor Inc. |
2 / 23 page X40626 REV 1.1.15 2/11/04 Characteristics subject to change without notice. 2 of 23 www.xicor.com operating level and stabilizes. Four industry standard Vtrip thresholds are available. However, Xicor’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s Block Lock™ Protection. The array is internally organized as 64 bytes per page. The device features an 2-wire interface and software protocol allowing operation on an I2C bus. The device utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 page write cycles and a minimum data retention of 100 years. PIN CONFIGURATION S1 VSS VCC V2MON WP 3 2 4 1 12 13 11 14 14 Pin SOIC/TSSOP S0 NC RESET 6 5 7 9 10 8 NC SDA SCL V2FAIL NC NC PIN FUNCTION Pin Name Function 1, 4, 6, 13 NC No Internal Connections 2S0 Device Select Input 3S1 Device Select Input 5 RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the min- imum VCC sense level for typically 200ms. RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time- out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET goes active on power up and remains active for typically 200ms after the power supply stabilizes. 7VSS Ground 8 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time-out period results in RESET going active. 9 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 10 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin. This circuit works independently from the Low VCC reset and battery switch circuits. Connect V2FAIL to VSS when not used. 11 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. There is no hysteresis in the V2MON comparator circuits. 12 WP Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control register. 14 VCC Supply Voltage |
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