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X9241A Datasheet(PDF) 11 Page - Xicor Inc. |
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X9241A Datasheet(HTML) 11 Page - Xicor Inc. |
11 / 18 page X9241A Characteristics subject to change without notice. 11 of 18 REV 1.1.13 12/09/02 www.xicor.com D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a poten- tiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (RH–RL)/63, single pot (4) Max. = all four arrays cascaded together, Typical = individual array resolutions. ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING POWER-UP REQUIREMENTS (Power Up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First Vcc, then the potentiometer pins. It is suggested that Vcc reach 90% of its final value before power is applied to the potentiometer pins. The Vcc ramp rate specification should be met, and any glitches or slope changes in the Vcc line should be held to <100mV if possible. Also, Vcc should not reverse polarity by more than 0.5V. Notes: (5) This parameter is guaranteed by characterization or sample testing. (6) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are guaranteed by design. (7) This parameter is guaranteed by design. (8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve. (9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to the device. Symbol Parameter Limits Unit Test Condition Min. Typ. Max. lCC Supply current (active) 3 mA fSCL = 100kHz, SDA = Open, Other Inputs = VSS ISB VCC current (standby) 200 500 µA SCL = SDA = VCC, Addr. = VSS ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC VIH Input HIGH voltage 2 VCC + 1 V VIL Input LOW voltage –1 0.8 V VOL Output LOW voltage 0.4 V IOL = 3mA Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 Years Symbol Parameter Max. Unit Test Condition CI/O (5) Input/output capacitance (SDA) 19 pF VI/O = 0V CIN (5) Input capacitance (A0, A1, A2, A3 and SCL) 12 pF VIN = 0V Symbol Parameter Min. Typ. Max. Unit tPUR (6) Power-up to initiation of read operation 1 ms tPUW (6) Power-up to initiation of write operation 5 ms tRVCC VCC Power up ramp rate 0.2 50 V/msec |
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