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S-19190AAH-M6T1U Datasheet(PDF) 11 Page - Seiko Instruments Inc |
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S-19190AAH-M6T1U Datasheet(HTML) 11 Page - Seiko Instruments Inc |
11 / 25 page FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.5_00 S-19190 Series 11 Test Circuit S-19190 Series VDD VSS DP CE _____ CO CB A A A RCB = 100 k Ω RCO = 100 k Ω V1 V2 V3 V4 V5 SW1 SW2 SW4 SW3 IVDD ICB ICO Figure 3 Caution Unless otherwise specified in Table 8, set V2 = V3 = 0 V, and SWn (n = 1 to 4) = OFF. 1. CE _____ pin voltage "H" CE _____ pin voltage "H" (VCE _____ H) is defined as the voltage at which IVDD is changed from IOPE to IPSV when V2 is increased from 0 V after setting V1 = VBL − 0.1 V. 2. CE _____ pin voltage "L" CE _____ pin voltage "L" (VCE _____ L) is defined as the voltage at which IVDD is changed from IPSV to IOPE when V2 is decreased from VBL − 0.1 V after setting V1 = V2 = VBL − 0.1 V. 3. DP pin voltage "H" *1 DP pin voltage "H" (VDPH) is defined as the voltage at which the test mode is switched when V3 is increased from 0 V after setting V1 = VBL − 0.1 V. 4. DP pin voltage "L" *1 DP pin voltage "L" (VDPL) is defined as the voltage at which the normal operation mode is switched when V3 is decreased from VBL − 0.1 V after setting V1 = V3 = VBL − 0.1 V. 5. Cell balancing detection delay time Cell balancing detection delay time (tBU) is defined as the time from when SW1 is set to ON and V1 is set to VBU − 0.1 V to when the CB pin output is inverted after setting V1 to VBU + 0.1 V. 6. Cell balancing release delay time Cell balancing release delay time (tBL) is defined as the time from when SW1 is set to ON and V1 is set to VBL + 0.1 V to when the CB pin output is inverted after setting V1 to VBL − 0.1 V. 7. Overcharge detection delay time Overcharge detection delay time (tCU) is defined as the time from when SW1 is set to ON and V1 is set to VCU − 0.1 V to when the CO pin output is inverted after setting V1 to VCU + 0.1 V. 8. Overcharge release delay time Overcharge release delay time (tCL) is defined as the time from when SW1 is set to ON and V1 is set to VCL + 0.1 V to when the CO pin output is inverted after setting V1 to VCL − 0.1 V. *1. For details about switching to the test mode by using the DP pin, refer to "5. DP pin" in " Operation". |
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