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S-19101N12A-N4T2U Datasheet(PDF) 11 Page - Seiko Instruments Inc |
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S-19101N12A-N4T2U Datasheet(HTML) 11 Page - Seiko Instruments Inc |
11 / 30 page FOR AUTOMOTIVE 125°C OPERATION VOLTAGE DETECTOR BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) Rev.1.0_01 S-19101xxxA Series 11 2. Delay circuit The delay circuit delays the output signal to the OUT pin from the time at which the power supply voltage (VDD) exceeds the release voltage ( +VDET) when the power supply voltage (VDD) is turned on. The output signal is not delayed when VDD decreases to the detection voltage ( −VDET) or less (refer to "Figure 13 Operation 2"). The delay time (tD) is determined by the time constant of the built-in constant current (approx. 100 nA) and the attached delay capacitor (CD), or the delay time (tD0) when the CD pin is open, and calculated from the following equation. When the CD value is sufficiently large, the tD0 value can be disregarded. tD [ms] = Delay coefficient × CD [nF] + tD0 [ms] Table 7 Delay Coefficient Operation Temperature Delay Coefficient Min. Typ. Max. Ta = +125°C 1.96 3.50 5.15 Ta = +105°C 2.58 3.70 5.40 Ta = +25°C 4.70 5.47 6.24 Ta = −40°C 5.64 8.40 12.01 Table 8 Delay Time Operation Temperature Delay Time (tD0) Min. Typ. Max. Ta = −40°C to +125°C 0.01 ms 0.10 ms 0.80 ms Caution 1. When the CD pin is open, a double pulse shown in Figure 14 may appear at release. To avoid the double pulse, attach 100 pF or more capacitor to the CD pin. Do not apply voltage to the CD pin from the exterior. VOUT Time Figure 14 2. Mounted board layout should be made in such a way that no current flows into or flows from the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be provided. 3. There is no limit for the capacitance of CD as long as the leakage current of the capacitor can be ignored against the built-in constant current value. Leakage current causes deviation in delay time. When the leakage current is larger than the built-in constant current, no release takes place. |
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