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GS81314LQ18GK-120 Datasheet(PDF) 4 Page - GSI Technology |
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GS81314LQ18GK-120 Datasheet(HTML) 4 Page - GSI Technology |
4 / 40 page GS81314LQ18/36GK-133/120/106 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.09 5/2016 4/40 © 2014, GSI Technology Pin Description Symbol Description Type SA[21:0] Address — Read address is registered on CK and write address is registered on CK. Input D[35:0] Write Data — Registered on KD and KD during Write operations. D[17:0] - x18 and x36. D[35:18] - x36 only. Input Q[35:0] Read Data — Aligned with CQ and CQ during Read operations. Q[17:0] - x18 and x36. Q[35:18] - x36 only. Output QVLD[1:0] Read Data Valid — Driven high one half cycle before valid read data. Output CK, CK Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing control, and for output timing control. Input KD[1:0], KD[1:0] Write Data Input Clocks — Dual single-ended. Used for latching write data inputs. KD0, KD0: latch D[17:0] in x36, and D[8:0] in x18. KD1, KD1: latch D[35:18] in x36, and D[17:9] in x18. Input CQ[1:0], CQ[1:0] Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs. Facilitate source-synchronous operation. CQ0, CQ0: align with Q[17:0] in x36, and Q[8:0] in x18. CQ1, CQ1: align with Q[35:18] in x36, and Q[17:9] in x18. Output R Read Enable — Registered on CK. See the Clock Truth Table for functionality. Input W Write Enable — Registered on CK. See the Clock Truth Table for functionality. Input MRW Mode Register Write — Registered on CK. Can be used synchronously or asynchronously to enable Reg- ister Write Mode. See the State and Clock Truth Tables for functionality. Input PLL PLL Enable — Weakly pulled High internally. PLL = 0: disables internal PLL. PLL = 1: enables internal PLL. Input RST Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High. Weakly pulled Low internally. Input ZQ Driver Impedance Control Resistor Input — Must be connected to VSS through an external resistor RQ to program driver impedance. Input ZT ODT Impedance Control Resistor Input — Must be connected to VSS through an external resistor RT to program ODT impedance. Input RCS Current Source Resistor Input — Must be connected to VSS through an external 2K resistor to provide an accurate current source for the PLL. Input |
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