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STK14C88-3 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part No. STK14C88-3
Description  32K x 8 AutoStore™ nvSRAM QuantumTrap CMOS Nonvolatile StaticRAM
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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STK14C88-3 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

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STK14C88-3
November 2003
4
Document Control # ML0015 rev 0.3
SRAM WRITE CYCLES #1 & #2
(VCC = 3.0V-3.6V)e
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be
≥ VIH during address transitions.
Note l:
HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
SRAM WRITE CYCLE #2: E Controlledk, l
NO.
SYMBOLS
PARAMETER
STK14C88-3-35
STK14C88-3-45
STK14C88-3-55
UNITS
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
12
tAVAV
tAVAV
tWC
Write Cycle Time
35
45
55
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
25
30
40
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
25
30
40
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
12
15
25
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
0
0
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
25
30
40
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
0
0
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0
0
0
ns
20
tWLQZi, j
tWZ
Write Enable to Output Disable
13
15
20
ns
21
tWHQX
tOW
Output Active after End of Write
5
5
5
ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
tAVAV
W
16
tWHDX
DATA IN
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DATA VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
DATA IN
12
tAVAV
16
tEHDX
13
tWLEH
19
tEHAX
18
tAVEL
17
tAVEH
DATA VALID
15
tDVEH
HIGH IMPEDANCE
14
tELEH
DATA OUT
E
ADDRESS
W
DATA IN


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