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SN74LV163A Datasheet(PDF) 2 Page - Texas Instruments

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Part No. SN74LV163A
Description  4BIT SYNCHRONOUS BINARY
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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SN74LV163A Datasheet(HTML) 2 Page - Texas Instruments

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SN54LV163A, SN74LV163A
4BIT SYNCHRONOUS BINARY COUNTERS
SCLS405F − APRIL 1998 − REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The ’LV163A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCC operation.
These synchronous, presettable counters feature an internal carry look ahead for application in high-speed
counting designs. The ’LV163A devices are 4-bit binary counters. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by
the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting
spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’LV163A devices is synchronous. A low level at the clear (CLR) input sets all four of
the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
LOAD
ENP
ENT
CLK
QA
QB
QC
QD
FUNCTION
L
X
X
X
X
L
L
L
L
Reset to “0”
H
LX
X
A
B
C
D
Preset data
H
H
X
L
No change
No count
H
H
L
X
No change
No count
H
H
H
H
Count up
Count
H
X
X
X
No change
No count


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